Implementation of a fully implantable middle-ear hearing device chip

Abstract

Background and objective: Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body.

Methods: In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory.

Results and conclusion: The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 μm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.

Keywords: CMOS process; Cadaver experiment; Fully implantable middle ear hearing device; Verilog-HDL; wide dynamic range.

Figure 1.

Block diagram of WDRC using FFT [34].

Figure 2.

Block diagram of the F-IMEHD.

Figure 3.

Simulation results obtained using the original FFT method: (a) input signal, (b) FFT results using the original method, (c) IFFT results using the original method, and (d) cross correlation with input signal and IFFT results using the original method.

Figure 4.

Simulation results obtained using the proposed FFT method: (a) input signal, (b) FFT results obtained using the proposed method, (c) IFFT results obtained- using the proposed method, and (d) cross correlation with input signal and IFFT results obtained using the proposed method.

Figure 5.

Block diagram of the designed signal processor for the F-IMEHD.

Figure 6.

Simulation results of channel separation: (a) input signal, (b) separated signal on channel 1, (c) separated signal on channel 2, (d) separated signal on channel 3, and (e) separated signal on channel 4.

Figure 7.

Simulation results of gain-applied IFFT: (a) input signal, (b) result of applying gain to input signal, (c) result of gain-applied IFFT using proposed method, (d) gain signal applied to channel 2, and (e) gain signal applied to channel 3.

Figure 8.

(a) Simulation results of the designed processing chip, and (b) enlarged graph on time axis of (a).

Figure 9.

The circuit of (a) SAR ADC and (b) class-D amplifier using Cadence spectre.

Figure 10.

The layout of (a) SAR ADC and (b) class-D amplifier using Cadence Virtuoso.

Figure 11.

The layout of designed chip using Cadence Virtuoso.

Figure 12.

(a) fabricated die chip micrograph, (b) top of packaged chip, and (c) bottom of packaged chip.

Figure 13.

(a) Schematic of the experiment, and (b) Image of the experiment.

Figure 14.

Experimental results.

Figure 15.

Images of (a) prototype system, (b) minimized test board, and (c) human cadaver experiments.

Figure 16.

Results of human cadaver experiments; (a) basic output characteristic with no gain, (b) comparison of gain characteristic for normal hearing loss and 50 dB hearing loss by FIG6 fitting rule.