Emulation of the BIS engine

Abstract

The operation of the BIS monitor remains undescribed, despite 20 years of clinical use and 3000 academic articles. The core algorithmic software (the BIS Engine) can be retrieved from the motherboard of the A-2000 monitor in binary form through forensic disassembly using debugging interfaces left in place by the original designers, opening the possibility of executing the BIS algorithms on contemporary computers through emulation. Three steps were required for emulation. Firstly, the monitor input stage monitor was disassembled to determine how EEG signals can be compatibly presented to the Engine. Secondly, the Digital Signal Processor on which the Engine executes was recreated in software. Thirdly, the Engine code was patched, allowing execution separated from monitor hardware. Code performance under noise load was evaluated. EEG signals and BIS variables were obtained from a 13-year-old child in normal physiological sleep using a modern BIS monitor. BIS values in sleeping children exhibit a wide dynamic range, including values nominally associated with clinical anesthesia, providing a risk-free technique to obtain empirical EEG data that broadly exercise the algorithms. Emulation demonstrated a correlation coefficient of R = 0.943, consistent with correlations between official Engine iterations. Additive white noise in the EEG caused a progressive lifting and flattening of BIS values. Emulation replicates BIS Engine behavior, allowing calculation upon existing EEG datasets or signals from other, potentially remote or wireless, devices. Emulation provides advantages for elucidating the mathematical expression of the algorithms, which remain important as practical constraints on any hypothetical mechanism of action of anesthetics.

Keywords: Biomedical engineering; Depth‐of‐anesthesia monitors; Emulation; Intraoperative monitoring; Processed EEG; Signal encoding.

Figure 1:

(A) The BIS XP Digital Signal Converter (DSC), which converts between the analog EEG signals measured from the patient’s forehead and a digital transmission stream to the main device. The DSC also provides electrical isolation between the patient and the device. (B) The DSC internal circuitry, which is constructed in a clamshell fashion with two circuit boards facing each other with three interconnection points between them. When assembled, this circuitry is wrapped in a flexible, conductive sheet which serves as a ground plane to block electrical interference. This sheet is removed in this image for visibility. (C) Opening the clamshell reveals that the circuitry is divided into a device side comprised primarily of digital circuitry, and a patient side comprised primarily of analog circuitry. Precision amplifiers are notable on the analog patient side for capturing EEG signals.

Figure 2:

(A) Block diagram of the digital input system of the BIS Engine for EEG data. For clarity, a one channel input is shown, though the system employs two systems in parallel to input two channels. The DSP receives a 1-bit datastream at 16384 Hz, which is subsequently downsampled by a factor of 128 and scaled to obtain input EEG waveforms in microvolts. The blocks highlighted in beige are implemented by the BIS Engine software as its input system. This input system can be driven by an emulated delta-sigma encoder, as shown, which produces a compatible bitstream from scaled EEG data. u(t) is the scaled EEG input data, v is the encoder feedback path, s_a is the cumulative sum at the first-stage of the encoder, s_b is the cumulative sum at the second-stage of the encoder. Δ produces the difference of its two inputs, and Σ produces the progressive, cumulative sum of its inputs. Respectively, u_min and u_max are the lower and upper bounds on input values. ũ(t) is the received EEG signal. (B) An example u(t) of a 128 Hz scaled EEG input waveform at 16-bit resolution over a duration of 15 seconds. The waveform is colored blue, as represented in the block diagram in Figure 2A. (C) The waveform in Figure 2B converted into its equivalent 16384 Hz delta-sigma bitstream. White intervals represent a digital 0 output and red intervals a digital 1, as represented in the block diagram in Figure 2A. (D) The bitstream in Figure 2C decoded back into microvolts using the digital input decimation and filtering employed by the BIS Engine, purple as shown in Figure 2A.

Figure 3:

(A) Rear aspect of the BIS Vista monitor showing the location of a USB-A port which can be used to record patient EEG and processed parameters to a study dataset. (B) An example study dataset recorded to a USB flash disk. The SPA file contains processed patient parameters in text format; the R2A file contains two channels of scaled EEG data stored, interleaved, as signed 16-bit integers. (C) Example output of the A-2000 BIS Engine emulator. As shown here, the BIS Engine software biseng.io for the TMS320C32 DSP processor is being run within the MAME emulator framework on a desktop computer, wholly divorced from the original hardware implementation.

Figure 4:

(A) Channel 1 BIS output from the A-2000 BIS Engine emulator (blue) and the processed output of the BIS Vista monitor at the time of acquisition (red). Note that the A-2000 and the Vista use different revisions of the BIS algorithm, and therefore small discrepancies between them is anticipated. (B) Correlation plot of the BIS value produced by the BIS Vista and the A-2000 emulator over the interval shown in Figure 4A. A linear fit has a gradient of almost unity, with a small shift in y-intercept. The values are very strongly correlated (Pearson R = 0.943. (C) Bland-Altman plot of agreement of the data shown in Figure 4B. Outward scatter at higher BIS values may represent revision of the behavior of the algorithm for light sedation, but there is tight agreement in the vicinity of BIS values for usual planes of general anesthesia. (D) A comparison of emulated BIS values in the presence of artificially superimposed common-mode white noise on the 2-channel input EEG signal. The black contour lines show the time-average of the emulated BIS value over the 225-minute time course.