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. 2021 Mar 19;12(3):328.
doi: 10.3390/mi12030328.

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Affiliations

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Young Suh Song et al. Micromachines (Basel). .

Abstract

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

Keywords: NOR flash memory; aluminum oxide; high-κ; nonvolatile charge-trapping memory; retention characteristic; stack engineering.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Schematic view illustrating (a) conventional TaN/Al2O3/HfO2/SiO2/Si (TAHOS), (b) bandgap engineered (BE)-TAHOS, and (c) proposed TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si (TAHOAOS) structure with two gate terminals. All structures commonly have HfO2 as charge-trapping layer (CTL) and Al2O3 as blocking oxide. The abbreviated letters T, A, H, O, N stand for tantalum nitride (TaN, gate metal), Al2O3, HfO2, SiO2, Si3N4, respectively.
Figure 2
Figure 2
(a) Illustration that summarizes overall workflow of this paper; (b) calibration results based on the fabricated TANOS device [45]; (c) another calibration result based on fabricated BE-TAHOS device [46]. (Sky blue dot line indicates the linear approximation of retention characteristic in the fabricated BE-TAHOS device.).
Figure 3
Figure 3
Basic transfer characteristics of three different device structures. These transfer characteristics show that our simulation is well designed with the same EOT thickness.
Figure 4
Figure 4
NOR array design for the proposed memory device structure. The newly added bottom gate line is perpendicular to the word line for selective programming.
Figure 5
Figure 5
(a) Change of electron charge trap density during programming at the cells of the proposed NOR array design. The density of trapped electron charge becomes saturated due to limited top gate voltage. In the selected cell, the higher top gate voltage may increase the saturated density of the trapped electron charge; (b) transfer characteristics just after programming of the cells in the proposed NOR array design; (c) cross-sectional view of the selected cell with TAHOS structure that illustrates the distribution of the trapped electron charge after programming.
Figure 6
Figure 6
(a) Top gate bias during programming and erasing, and (b) retention characteristics of the conventional TAHOS, BE-TAHOS, and the proposed TAHOAOS structure. The high top gate voltage (17 V for programming and −21 V for erasing) is applied in order to perform fair comparison by matching initial threshold voltage at 1 micro-second. (Specifically, programming with top gate voltage of 13 V, as in Table 2, results in different initial threshold voltage [37], and hence programming with a higher top gate voltage of 17 V is performed for fair comparison.).
Figure 7
Figure 7
Detailed description of retention characteristics in (a) conventional TAHOS, (b) BE-TAHOS, and (c) proposed TAHOAOS structure.
Figure 8
Figure 8
Energy band diagram of (a) BE-TAHOS, and (b) proposed TAHOAOS structure. Regarding retention characteristics, the valence band offset of BE-TAHOS (green arrow in panel a) mitigates the advantage of thicker tunneling oxide layers in BE-TAHOS. The abbreviated letters T, A, H, O, N stand for tantalum nitride (TaN, gate metal), Al2O3, HfO2, SiO2, Si3N4, respectively.
Figure 9
Figure 9
Enhancement of retention characteristics by the proposed tunneling oxide engineering. The graphs are calculated after 10 years of programming and erasing.

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