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. 2021 May 12;32(31).
doi: 10.1088/1361-6528/abfb99.

GaN-based complementary inverter logic gate using InGaN/GaN superlattice capped enhancement-mode field-effect-transistors

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GaN-based complementary inverter logic gate using InGaN/GaN superlattice capped enhancement-mode field-effect-transistors

Jaya Jha et al. Nanotechnology. .

Abstract

GaN-based high electron mobility transistors (HEMTs) have received much attention due to their potential usage in radio-frequency and high power applications. However, the development of logic gates has remained mostly elusive due to the still challenging reliable operation of the field-effect enhancement-mode n-transistor and nascent stage for the p-transistor. The n-transistor behavior is mainly achieved by combining the aggressive thinning down of the barrier layer, using charged oxides, and p-doping the cap layer. The p-transistor generally requires a heavily doped p-GaN layer. The realization of both transistors on the same substrate remains challenging due to the conflicting requirements for n- and p-transistors. Here, we propose a GaN-based field-effect complementary transistor device using a p-doped InGaN/GaN superlattice (SL) structure on top of the barrier layer of the HEMT heterostructure. The SL structure changes the electrostatics of the heterostructure by the formation of a two-dimensional hole gas region. An undoped SL structure is shown to be enough to lift the conduction band-edge above the Fermi level to convert the n-transistor from depletion-mode (D-mode) to enhancement-mode (E-mode). The lifting of the bands, in turn, creates a natural quantum-well for the holes in the p-transistor. An additional p-doping of the SL moves the threshold voltage of the E-mode n-transistor further into a positive direction and increases the hole density in the quantum-well E-mode p-transistor. The SL structure, which can be grown by a standard epitaxial process, facilitates the realizations of both the n- and p-transistors. The characteristics of individual devices are further analyzed. A digital inverter gate is simulated, and critical static and dynamic performance parameters are reported. The propagation delay indicates that logic operations can be done at a very high speed compared to those offered by other conventional semiconductors.

Keywords: CMOS; GaN CMOS; GaN nanotechnology; InGaN/GaN superlattice; gallium nitride; high electron mobility transistors; logic device.

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