Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach

Abstract

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly. To create nanopatterned Si feature arrays, a block-copolymer-assisted hard mask approach was utilized using a topographically patterned substrate with well-defined Si₃N₄ features for graphoepitaxially alignment of the self-assembled patterns. Microphase-separated long-range ordered polystyrene-b-poly(ethylene oxide) (PS-b-PEO) block-copolymer-derived dot and line nanopatterns were achieved by a thermo-solvent approach within the substrate topographically defined channels of various widths and lengths. Solvent annealing parameters (temperature, annealing time, etc.) were varied to achieve the desired patterns. The BCP structures were modified by anhydrous ethanol to facilitate insertion of iron oxide features within the graphoepitaxial trenches that maintained the parent BCP arrangements. Vertical and horizontal ordered Si nanowire structures within trenches were fabricated using the iron oxide features as hard masks in an inductively coupled plasma (ICP) etch process. Cross-sectional micrographs depict wires of persistent width and flat sidewalls indicating the effectiveness of the mask. The aspect ratios could be varied by varying etch times. The sharp boundaries between the transistor components was also examined through the elemental mapping.

Keywords: block copolymer; gate-all-around; graphoepitaxy; hard mask; nanowire.

Scheme 1. Design of the Graphoepitaxial Substrate

Scheme 2. Processing Steps for Fabricating Si Nanowires Arrays within the Trenches

(A) Graphoepitaxial substrate with channels of 7 nm silica-coated Si and SiN top sidewalls. (B) Spin-coated BCP film within channel. Hexagonally arranged PEO cylinders (CI) parallel and (CII) perpendicular to the substrate in PS matrix after solvent annealing. (DI and II) Modification of PEO cylinders creates nanoporous templates for the metal ion inclusion. Iron oxide horizontal (EI) and vertical (EII) nanowires were prepared by spin coating a metal ion precursor solution followed by UV/ozone treatment. Horizontal (FI) and vertical (FII) Si nanowires with iron oxide at the top by consecutive silica and silicon ICP etch. Horizontal (GI) and vertical (GII) Si nanowires with a silica layer at top after removal of oxide masks.

Figure 1

Arrays of BCP (42k–11.5k) dot patterns within trenches of the SiN substrate solvent annealed in toluene at 50 °C for 1 h with trench widths of (a) 45 nm, (b) 90 nm, (c) 135 nm, (d) 180 nm, (e) 225 nm, and (f) 270 nm, respectively.

Figure 2

Arrays of BCP (42k–11.5k) patterns within trenches of SiN substrate solvent annealed in toluene at 60 °C for 1 h with trench widths of (a) 45 nm, (b) 90 nm, (c) 135 nm, (d) 180 nm, and (e) 270 nm, respectively. Mixture of dots and line patterns of BCP solvent annealed in toluene at 60 °C for different times of (f) 1 h 30 min, (g) 2 h, and (h) 3 h, respectively.

Figure 3

Iron oxide (a,b, c) dot patterns and (d, e, f) line patterns using different kinds of BCP templates through the inclusion method.

Figure 4

Si (a,b, c) vertical and (d, e) horizontal nanowires and (f) vertical and horizontal nanowires patterns together after pattern transfer using iron oxide as a hard mask.

Figure 5

FIB cross sectioned TEM images of Si (a, b, c) vertical and (d, e) horizontal nanowire patterns with iron oxide at top for different etch times of (a, b, d, e) 30 s and (c) 1 min.

Figure 6

EDAX mappings of Si (a, b) 1 and 2 vertical and (c) 3 horizontal nanowire patterns with iron oxide at the top for different etch times of (a) 1 min, (b) 30 s, and (c) 1 min 30 s. (d) EDX spectrum obtained from the Si vertical nanowire arrays.