Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference

Abstract

Minimizing the variation in threshold voltage (V_t) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize V_t variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., L_g: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

Keywords: NAND flash memory; Technology Computer Aided Design (TCAD) simulation; disturbance; interference; non-volatile memory (NVM); program.

Figure 1

(a) Vertical NAND (VNAND) Flash cell array schematic showing neighbors both intra-string (Z-interference) and inter-string. Z-interference is the most critical since the channel is shared in close proximity for VNAND products. (b) Current versus voltage data as a function of the gate voltage of the victim cell (WL3). Solid line represents the reference state before the aggressor cell is programmed. Red dashed line and blue solid line denote the states after interference by T-B and B-T, respectively. (c) Interference of 8 different states (E, P1, P2, P3, P4, P5, P6, and P7) for triple level cell (TLC) under the condition of the aggressor programmed to P7 (V_t = 3.177 V). Blue diamonds and red circles show the results out of Bottom to Top (B-T, WL4 is aggressor) and Top to Bottom (T-B, WL2 is aggressor), respectively. Remarks with (Exp.) denote experimentally measured interferences (unpublished) from Samsung’s 4th generation VNAND (Ref. [18]).

Figure 2

(a) Net charge concentration (Q_CON) comparison of B-T and T-B. (b) Q_CON in the trap-nitride layer of WL3 as a function radial coordinate r, where 46.5 nm and 52.5 nm represent two interfaces with oxide layers: top, EP7, where WL3 is originally at the state with V_t = −3.889 V (E). Slight change in Q_CON for 46.5 < r (nm) < 46.7 is observed after interference, because of pass disturb (8 V); bottom, P1P7, where WL3 is initially at the state with V_t = −0.976 V (P1). In this case, pass disturb is negligible because P1 state is relatively invulnerable to V_PASS = 8 V.

Figure 3

Band diagram of the victim cell (WL3) along the radial direction of a cylindrical cell string and corresponding number of trapped charges in the trap-nitride layer as a function of time while programming WL2 with V_PGM = 16 V and V_PASS = 8 V. (a) WL3 at the state E exhibits Fowler–Nordheim tunneling due to lowered conduction band edge by trapped hole charges in the trap-nitride layer. (b) WL3 at the state P1 depicts the harsher tunneling barrier compared to that of E in Figure 4a. This is because the net charge in the trap-nitride layer is less positive compared to E(erase) state so that the electrostatic potential is higher. (c) Number of trapped charges (Q) in the trap-nitride layer of WL2 beginning from the state E as a function of time under programming voltage V_PGM = 16 V is shown (green dotted line) together with that of victim cell under two different states (E and P1). (d) WL3 at E under the bias V_PASS = 8 V shows the charge in Q from +792 to +771, implying about 20 electrons were tunneled and holes were canceled. (e) WL3 at P1 shows negligible change in Q (from +201 to +200) so that the interference (121 mV for B-T and 88 mV for T-B) purely comes from the adjacent cell’s channel inversion.

Figure 4

Poly-silicon channel information during reading operation (V_WL3 = −1 V, V_READ = 7 V, V_BL = 0.7 V, V_CSL = 0 V) (a) band diagram: Top, electron carrier concentration; bottom, following the z-axis (r = 38 nm). The potential of 0.7 V through the bit line is mainly applied to the reading cell (WL3) since the adjacent cells are fully inverted with V_READ = 7 V; hence they have negligible resistances. Consequently, WL4 should experience less inversion (by V_READ − 0.7 V = 6.3 V) compared to WL2 (by V_READ − 0 V = 7 V), which is reflected in electron density in the bottom figure. WL4 and WL2 have carriers of 1.3 and 1.9 (10¹⁸ cm⁻³) at the center, respectively. (b) Color plots of electron density for ‘initial’ reveal non-centered carrier bottleneck due to drain-induced-barrier-lowering (DIBL) effect. As a result, B-T; having the upper adjacent cell programmed, has the stronger interference compared to T-B with the lower adjacent cell programmed. The light blue region corresponds to trap-nitride layer (Si₃N₄) (c) When V_READ is increased to 8 V, the imbalance between B-T (V_READ − 0.7 V = 7.3 V) and T-B (V_READ − 0 = 8 V) is reduced.

Figure 5

Averaged interference (P1P7, P2P7, …, P6P7, and P7P7) for T-B and B-T schemes with various changes such as (a) V_READ, and cell dimensions, (b) gate length and (c) gate space, for the next generation vertical NAND Flash products. Note that the reference is (V_READ, L_g, L_s) = (7 V, 31 nm, 20 nm) and the raw data of each case is available in Figure S1.

Figure 6

Electrostatic potential distribution change with L_g scaling (31 → 24 nm) Both are after EP7 interference (V_t,Victim = −0.99 V, V_t,Aggressor = 3.2 V) followed by reading at the moment at V_WL3 = −1 V.