Silicon Nanowires: A Breakthrough for Thermoelectric Applications

Abstract

The potentialities of silicon as a starting material for electronic devices are well known and largely exploited, driving the worldwide spreading of integrated circuits. When nanostructured, silicon is also an excellent material for thermoelectric applications, and hence it could give a significant contribution in the fundamental fields of energy micro-harvesting (scavenging) and macro-harvesting. On the basis of recently published experimental works, we show that the power factor of silicon is very high in a large temperature range (from room temperature up to 900 K). Combining the high power factor with the reduced thermal conductivity of monocrystalline silicon nanowires and nanostructures, we show that the foreseen figure of merit ZT could be very high, reaching values well above 1 at temperatures around 900 K. We report the best parameters to optimize the thermoelectric properties of silicon nanostructures, in terms of doping concentration and nanowire diameter. At the end, we report some technological processes and solutions for the fabrication of macroscopic thermoelectric devices, based on large numbers of silicon nanowire/nanostructures, showing some fabricated demonstrators.

Keywords: figure of merit; silicon nanowire; thermal conductivity; thermoelectricity.

Figure 1

Available experimental data of the Seebeck coefficient are reported both for n-doping (Panel (a)) and for p-doping (Panel (b)). The logarithmic fit (see text) is also shown. The red lines show the Seebeck coefficient calculated with the Stratton formula (both for n and for p doping): experimental measurement give higher values of the Seebeck coefficient. Panel (a) is a modification of the figure published on [14].

Figure 2

The room temperature power factor $$S^2\sigma$$ is reported as a function of the doping concentration, both for n (Panel (a)) and for p type silicon (Panel (b)). An optimal doping for the maximum power factor is established both for n ($$n=5.5\times {10}^{25}$$ m$${}^{-3}$$) and for p ($$p=1.2\times {10}^{26}$$ m$${}^{-3}$$) type silicon. Panel (a) has been reprinted from [14] with permission.

Figure 3

The power factor of n (Panel (a)) and p (Panel (b)) doped silicon is reported as a function of temperature. The blue curves concern the doping concentration, which maximizes the power factor at room temperature, the red curves have been calculated considering $$S=S\left(T\right)$$ experimentally determined by Ohishi [12] for doping concentrations different from that for the maximum power factor.

Figure 4

The electrical conductivity for $$n=5.5\times {10}^{25}$$ m$${}^{-3}$$, normalized with respect to the bulk value, is reported as a function of the nanowire width (continuous curve). Furthermore, the experimental measurements of the thermal conductivity (scatters) are reported. For diameters between 30 nm and 100 nm (roughly), the electrical conductivity is comparable with that in the bulk, the thermal conductivity results were instead strongly reduced for sufficiently rough nanowires.

Figure 5

The factor Z (Panel (a)) and the figure of merit $$ZT$$ (Panel (b)) are reported as a function of temperature, for the optimum thermoelectric doping of n type silicon. Different curves consider different values of the thermal conductivity $$k_t$$. The highest values of Z are related to $$k_t=2$$ W/(m K), achievable in rough silicon nanowires.

Figure 6

Original SEM micrographs of fabricated prototypes, together with a sketch of these planar thermoelectric devices. These prototypes confirm the feasibility of an all-silicon thermoelectric device, based on large arrays of silicon nanostructures.

Figure 7

Sketches and SEM micrographs of thermoelectric devices based on silicon nanowires fabricated perpendicular to the substrate.