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. 2021 Sep 25;12(10):1152.
doi: 10.3390/mi12101152.

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Fei Chen  1 , Bo Chen  1 , Hongzhe Lin  1 , Yachen Kong  1 , Xin Liu  1 , Xuepeng Zhan  1   2 , Jiezhi Chen  1
Affiliations

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Fei Chen et al. Micromachines (Basel). .

Abstract

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (-30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells' degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

Keywords: 3D NAND flash memory; endurance; read disturb; temperature.

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Conflict of interest statement

The authors declare that there is no conflict of interest.

Figures

Figure 1
Figure 1
(a) A schematic of a 2D NAND string and a 3D NAND string, wherein a 3D NAND cell unit contains core oxide, poly-Si channel, tunneling layer, CT layer, blocking layer, a and control gate; (b) TLC operations by storing 3 bits in each cell at three pages: MSB, CSB, and LSB; V1~V7 denote read voltages with the definitions of Vth down-shift and up-shift errors.
Figure 2
Figure 2
Measured operation times during P/E cycling at different temperatures: (a) erase time (terase) and (b) program time (tprog). terase depends on the temperature, while tprog depends on both the temperature and P/E cycles, which agreed well with the simulation curves in the blocks with higher than 100 P/E cycles.
Figure 3
Figure 3
(a) Measured RBER with P/E cycling at different temperatures; (b) normalized RBER to study RBER degradation.
Figure 4
Figure 4
Cross-temperature characterizations to study degradation at various temperatures. The first and third stages were fixed to 25 °C, while the second stage selected three different temperatures, −30, 25, and 70 °C. The RBER was normalized by the first point of the RBER to compare the degradation trends of each condition.
Figure 5
Figure 5
Read disturb characterizations at different temperatures from −30 to 70 °C.
Figure 6
Figure 6
Read disturb-related RBER changes were divided into (a) down-shift errors and (d) up-shift errors from −30 to 70 °C; (b,c) compares B-to-A errors and G-to-F down-shift errors, respectively, while (e,f) compares A-to-B errors and F-to-G up-shift errors, respectively, at −30, 25, and 70 °C.
Figure 7
Figure 7
Measured fail bit count (FBC) of different program levels: error bits from (a) D-to-E; (b) E-to-F; (c) F-to-G.
See this image and copyright information in PMC

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