A Dynamic Threshold Cancellation Technique for a High-Power Conversion Efficiency CMOS Rectifier

Abstract

Power conversion efficiency (PCE) has been one of the key concerns for power management circuits (PMC) due to the low output power of the vibrational energy harvesters. This work reports a dynamic threshold cancellation technique for a high-power conversion efficiency CMOS rectifier. The proposed rectifier consists of two stages, one passive stage with a negative voltage converter, and another stage with an active diode controlled by a threshold cancellation circuit. The former stage conducts the signal full-wave rectification with a voltage drop of 1 mV, whereas the latter reduces the reverse leakage current, consequently enhancing the output power delivered to the ohmic load. As a result, the rectifier can achieve a voltage and power conversion efficiency of over 99% and 90%, respectively, for an input voltage of 0.45 V and for low ohmic loads. The proposed circuit is designed in a standard 130 nm CMOS process and works for an operating frequency range from 800 Hz to 51.2 kHz, which is promising for practical applications.

Keywords: CMOS rectifier; dynamic threshold cancellation technique; high power conversion efficiency; power management circuit; vibration energy harvester.

Figure 1

Schematic of the proposed active rectifier composed by a NVC and an active diode controlled by a threshold cancellation circuit.

Figure 2

Schematic of the two-input common gate comparator CMP.

Figure 3

Physical layout of the proposed CMOS rectifier.

Figure 4

Simulated waveforms of the rectifier for $${\mathrm{R}}_{\mathrm{LOAD}}=5.5 \mathrm{k}\Omega$$ and $${\mathrm{C}}_{\mathrm{LOAD}}=2 \mu \mathrm{F}$$.

Figure 5

VCE versus input voltage amplitude simulated for different ohmic loads.

Figure 6

Simulated comparator behavior in steady state for $${\mathrm{R}}_{\mathrm{LOAD}}=500 \Omega$$ and $${\mathrm{C}}_{\mathrm{LOAD}}=2 \mu \mathrm{F}$$.

Figure 7

PCE versus input voltage amplitude simulated for different values of $${\mathrm{R}}_{\mathrm{LOAD}}$$

Figure 8

VCE and PCE features with the variation of the width of the NVC transistors and M5 (L = 0.13 µm).

Figure 9

PCE versus input voltage amplitude simulated for different input frequencies for $${\mathrm{R}}_{\mathrm{LOAD}}=5.5 \mathrm{k}\Omega$$

Figure 10

PCE variation with temperature depending on the process corner variation for a $${\mathrm{R}}_{\mathrm{LOAD}}=5.5 \mathrm{k}\Omega$$