Vertically Aligned n-Type Silicon Nanowire Array as a Free-Standing Anode for Lithium-Ion Batteries

Abstract

Due to its high theoretical specific capacity, a silicon anode is one of the candidates for realizing high energy density lithium-ion batteries (LIBs). However, problems related to bulk silicon (e.g., low intrinsic conductivity and massive volume expansion) limit the performance of silicon anodes. In this work, to improve the performance of silicon anodes, a vertically aligned n-type silicon nanowire array (n-SiNW) was fabricated using a well-controlled, top-down nano-machining technique by combining photolithography and inductively coupled plasma reactive ion etching (ICP-RIE) at a cryogenic temperature. The array of nanowires ~1 µm in diameter and with the aspect ratio of ~10 was successfully prepared from commercial n-type silicon wafer. The half-cell LIB with free-standing n-SiNW electrode exhibited an initial Coulombic efficiency of 91.1%, which was higher than the battery with a blank n-silicon wafer electrode (i.e., 67.5%). Upon 100 cycles of stability testing at 0.06 mA cm^-2, the battery with the n-SiNW electrode retained 85.9% of its 0.50 mAh cm^-2 capacity after the pre-lithiation step, whereas its counterpart, the blank n-silicon wafer electrode, only maintained 61.4% of 0.21 mAh cm^-2 capacity. Furthermore, 76.7% capacity retention can be obtained at a current density of 0.2 mA cm^-2, showing the potential of n-SiNW anodes for high current density applications. This work presents an alternative method for facile, high precision, and high throughput patterning on a wafer-scale to obtain a high aspect ratio n-SiNW, and its application in LIBs.

Keywords: Li-ion battery; n-type silicon anode; nanowire array; silicon anode; silicon nanowire.

Figure 1

Schematic of the processing steps to fabricate the n-SiNW. (a) Preparation and cleaning of the Si wafer. (b) Spin coating of the photoresist on the wafer. (c) Circular photoresist pattern formation after photolithography. (d) ICP-RIE at cryogenic temperature resulting in an n-SiNW. (e) Mechanism of the etching process by ICP-RIE. (f) Photoresist removal and mechanical dicing to obtain a die area of 1 × 1 cm².

Figure 2

Top-down fabricated n-SiNW anode with an aspect ratio of ~10 compared to an unstructured n-Si substrate. Top view of SEM images for (a) plain/blank Si substrate and (b) n-SiNW. (c) The cross-sectional view of the free-standing n-SiNW anode (inset: the actual die dimensions of the n-SiNW anode). (d) X-ray diffraction (XRD) patterns of an n-SiNW and a plain/blank n-type Si wafer.

Figure 3

Galvanostatic discharge and charge profiles of the half-cell LIBs with plain/blank n-Si wafer and n-SiNW electrode. (a) Pre-lithiation cycle and (b) 2nd to 100th cycles of a LIB with blank n-Si wafer electrode. (c) Pre-lithiation cycle and (d) 2nd to 100th cycles of LIBs with n-SiNW electrode.

Figure 4

Electrochemical performances of LIBs with blank n-Si wafer or n-SiNW electrodes. Discharge–charge capacities and the corresponding Coulombic efficiencies at a current density of 0.06 mA cm⁻² for 100 cycles of the batteries with (a) a blank n-Si wafer or (b) an n-SiNW electrode. (c) Capacity retention of LIBs with blank Si wafer and n-SiNW electrodes cycled at 0.02, 0.05, 0.1, and 0.2 mA cm⁻².

Figure 5

Electrochemical impedance spectroscopy (EIS) analysis of half-cell LIBs with blank n-Si wafer and n-SiNW electrodes after pre-lithiation cycles. (a) Nyquist plots of the cells with blank n-Si wafer and n-SiNW electrodes. The inset image is the equivalent circuit model used for fitting the EIS results. (b) Phase angle diagram of the cells with blank n-Si wafer and n-SiNW electrodes.