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. 2021 Dec 30;12(1):49.
doi: 10.3390/membranes12010049.

Improving Device Characteristics of Dual-Gate IGZO Thin-Film Transistors with Ar-O2 Mixed Plasma Treatment and Rapid Thermal Annealing

Affiliations

Improving Device Characteristics of Dual-Gate IGZO Thin-Film Transistors with Ar-O2 Mixed Plasma Treatment and Rapid Thermal Annealing

Wei-Sheng Liu et al. Membranes (Basel). .

Abstract

In this study, high-performance indium-gallium-zinc oxide thin-film transistors (IGZO TFTs) with a dual-gate (DG) structure were manufactured using plasma treatment and rapid thermal annealing (RTA). Atomic force microscopy measurements showed that the surface roughness decreased upon increasing the O2 ratio from 16% to 33% in the argon-oxygen plasma treatment mixture. Hall measurement results showed that both the thin-film resistivity and carrier Hall mobility of the Ar-O2 plasma-treated IGZO thin films increased with the reduction of the carrier concentration caused by the decrease in the oxygen vacancy density; this was also verified using X-ray photoelectron spectroscopy measurements. IGZO thin films treated with Ar-O2 plasma were used as channel layers for fabricating DG TFT devices. These DG IGZO TFT devices were subjected to RTA at 100 °C-300 °C for improving the device characteristics; the field-effect mobility, subthreshold swing, and ION/IOFF current ratio of the 33% O2 plasma-treated DG TFT devices improved to 58.8 cm2/V·s, 0.12 V/decade, and 5.46 × 108, respectively. Long-term device stability reliability tests of the DG IGZO TFTs revealed that the threshold voltage was highly stable.

Keywords: dual-gate thin-film transistor (DG TFT); indium–gallium–zinc oxide (IGZO); plasma treatment.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Schematic of an IGZO TFT with DG design.
Figure 2
Figure 2
High-resolution O 1s XPS spectra with curve-fitting results obtained for IGZO thin films: (a) pristine sample and (b) sample A, (c) sample B, and (d) sample C.
Figure 3
Figure 3
Hall measurement results of the pristine sample and samples A, B, and C.
Figure 4
Figure 4
AFM images for the (a) pristine sample and samples (b) A, (c) B, and (d) C. (e). Surface RMS roughness measured for the pristine sample and samples A, B, and C.
Figure 5
Figure 5
(a) IDS–VGS transfer characteristics of SG TFTs with a 33% O2 plasma–treated IGZO channel layer and annealed at temperatures from RT to 300 °C. (b) Energy band diagrams for the SG TFTs before and after the thermal annealing process.
Figure 6
Figure 6
(a) IDS–VGS transfer characteristics of a DG TFT with a 33% O2 plasma–treated IGZO channel layer and annealed at temperatures of 100, 200, and 300 °C. (b) Energy band diagrams for the DG TFTs before and after the thermal annealing process.
Figure 7
Figure 7
IDS–VDS output characteristics of a DG TFT annealed at (a) 100 °C, (b) 200 °C, and (c) 300 °C.
Figure 8
Figure 8
Evolution of transfer characteristics of DG IGZO TFTs with negative bias stress of −10 V for TFTs annealed at (a) 100 °C, (c) 200 °C, and (e) 300 °C and with positive bias stress of 10 V for TFTs annealed at (b) 100 °C, (d) 200 °C, and (f) 300 °C, respectively.
Figure 9
Figure 9
(a) The ΔVTH of DG IGZO TFTs with PBS and NBS tests for TFT from the initial condition to the annealed condition at 300 °C. The energy band diagrams for the DG TFTs before and after NBS and PBS tests are shown in (bd), respectively.

References

    1. Baek G., Bie L., Abe K., Kumomi H., Kanicki J. Electrical instability of double-gate a-IGZO TFTs with metal source/drain recessed electrodes. IEEE Trans. Electron Devices. 2014;61:1109–1115. doi: 10.1109/TED.2014.2307352. - DOI
    1. Cao Q., Kim H.S., Pimparkar N., Kulkarni J.P., Wang C., Shim M., Roy K., Alam M.A., Rogers J.A. Rogers, Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature. 2008;454:495–500. doi: 10.1038/nature07110. - DOI - PubMed
    1. Lin C.L., Chang W.Y., Hung C.C. Compensating pixel circuit driving AMOLED display with a-IGZO TFTs. IEEE Electron Device Lett. 2013;34:1166–1168. doi: 10.1109/LED.2013.2271783. - DOI
    1. Seok M.J., Choi M.H., Mativenga M., Geng D., Kim D.Y., Jang J. A full-swing a-IGZO TFT-based inverter with a top-gate-bias-induced depletion load. IEEE Electron Device Lett. 2011;32:1089–1091. doi: 10.1109/LED.2011.2157798. - DOI
    1. Kang D.H., Kang I., Ryu S.H., Jang J. Self-aligned coplanar a-IGZO TFTs and application to high-speed circuits. IEEE Electron Device Lett. 2011;32:1385–1387. doi: 10.1109/LED.2011.2161568. - DOI