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Review
. 2022 Jan 18;24(2):139.
doi: 10.3390/e24020139.

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Affiliations
Review

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Luca Crocetti et al. Entropy (Basel). .

Abstract

In the cybersecurity field, the generation of random numbers is extremely important because they are employed in different applications such as the generation/derivation of cryptographic keys, nonces, and initialization vectors. The more unpredictable the random sequence, the higher its quality and the lower the probability of recovering the value of those random numbers for an adversary. Cryptographically Secure Pseudo-Random Number Generators (CSPRNGs) are random number generators (RNGs) with specific properties and whose output sequence has such a degree of randomness that it cannot be distinguished from an ideal random sequence. In this work, we designed an all-digital RNG, which includes a Deterministic Random Bit Generator (DRBG) that meets the security requirements for cryptographic applications as CSPRNG, plus an entropy source that showed high portability and a high level of entropy. The proposed design has been intensively tested against both NIST and BSI suites to assess its entropy and randomness, and it is ready to be integrated into the European Processor Initiative (EPI) chip.

Keywords: ASIC; EPI; FPGA; entropy; random number generator.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Internal architecture of RNG engine.
Figure 2
Figure 2
Internal architecture of entropy source module of RNG engine (a), and of FiGaRO stages composing it (b).
Figure 3
Figure 3
Internal architecture of DRBG module of RNG engine.
Figure 4
Figure 4
Schematic of a GaRO with enable (en signal) and W inverting elements.
Figure 5
Figure 5
Typical outcome of the synthesis of a GaRO. This schematic has been extracted by using the Synopsys Design Compiler tool.
Figure 6
Figure 6
Outcome of GaRO synthesis with proper constraints. This schematic has been extracted by using the Synopsys Design Compiler tool and refers to the synthesis of the same RTL code used also for the synthesis of the circuit represented in Figure 5 but including dedicated synthesis constraints.
Figure 7
Figure 7
Graph of NIST STS PR metric results for tested DRBG sequences. The dark golden points represent the PR values for each test, or sub-test, and the blue dashed lines represent the boundaries of the confidence interval(s): it the PR value lies outside the confidence interval(s), the test is failed: three (six) failing tests are tolerated for the widest (narrowest) confidence interval.
Figure 8
Figure 8
Graph NIST STS PoP metric results for tested DRBG sequences. The dark golden points represent the PoP values for each test, and the light blue dashed line traces the threshold for the pass–fail criterion: if the PoP value is greater than (or equal to) threshold, then the test is passed; otherwise, it is failed. The vertical axis uses the logarithmic scale.
Figure 9
Figure 9
Histograms of p-values distributions from NIST STS tests. The three-dimensional histograms of the distribution of p-values are reported only for single-experiment tests of NIST STS and, according to the results of PoP metric (Figure 8), their uniformity can be noted.

References

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