Emulation of synaptic functions with low voltage organic memtransistor for hardware oriented neuromorphic computing

Abstract

Here, various synaptic functions and neural network simulation based pattern-recognition using novel, solution-processed organic memtransistors (memTs) with an unconventional redox-gating mechanism are demonstrated. Our synaptic memT device using conjugated polymer thin-film and redox-active solid electrolyte as the gate dielectric can be routinely operated at gate voltages (V_GS) below - 1.5 V, subthreshold-swings (S) smaller than 120 mV/dec, and ON/OFF current ratio larger than 10⁸. Large hysteresis in transfer curves depicts the signature of non-volatile resistive switching (RS) property with ON/OFF ratio as high as 10⁵. In addition, our memT device also shows many synaptic functions, including the availability of many conducting-states (> 500) that are used for efficient pattern recognition using the simplest neural network simulation model with training and test accuracy higher than 90%. Overall, the presented approach opens a new and promising way to fabricate high-performance artificial synapses and their arrays for the implementation of hardware-oriented neural network.

Figure 1

(a) Schematic diagram of the redox-electrolyte gated thin-film memtransistor (memT) including the details of the pulse and sweep measurement protocol. (b) Schematic representation of the voltage pulses at the gate terminal and DC voltage sweep across source-drain (S-D) contacts to measure the channel conductivity of the fabricated 3-terminal memT devices. (c, d) Show multiple discrete conducting states of the device channel measured after applying different voltage pulse amplitudes (V_GS) and widths (t_w), respectively.

Figure 2

(a) Schematic diagram of the memT devices to study EPSC potentiation and retention by varying presynaptic voltage pulse numbers up to 25 pulses. (b) Potentiation and retention of EPSC result with increasing number of consecutive presynaptic pulses (− 3.0 V, 2 s) at the gate. (c) Dependency of the relaxation time in terms of natural decay of EPSC in open circuit mode to the off-conducting state on number of consecutive pulses applied at the gate.

Figure 3

(a) Presynaptic pulse width (t_w) dependent variation of the EPSC response to demonstrate spike-width-dependent plasticity (SWDP). 25 write pulses (− 3.0 V) followed by 25 erase pulses (+ 3.0 V) were consecutively applied at the gate by varying t_w from 50 to 2000 ms. Insets, enlarged portion of the obtained curves to show the potentiation of EPSC for each of the incoming pulses. (b) Variation of the synaptic potentiation ratio (SPR) calculated from the two consecutive write (W) pulses for every pulse widths as obtained in (a). (c) Dependency of the sequential paired-pulse facilitation (SPPF) of synaptic weight on pulse widths and numbers as estimated from the results shown in (a).

Figure 4

(a) Schematic representation of neural connectivity via synapse in a biological brain for the action potential transmission. (b) Short-term potentiation by applying a pair of presynaptic spikes (V_GS =  − 3.0 V) with Δt of 2 s. Postsynaptic currents (I_post) were recorded by biasing the drain at − 0.5 V. (c) Paired pulse facilitation (PPF) of the synaptic memT devices obtained by varying the time interval Δt from 100 to 10 s.

Figure 5

Synaptic weight changes estimated STDP (ΔW %) for both of negative and positive time delays (± Δt) with a postsynaptic read (− 2.0 V, 10 ms) pulse before and after paired pulse propagation. Insets, schematic representation of temporally correlated presynaptic (− 3.0 V, 2 s) and postsynaptic (− 3.0 V, 2 s) pulses for both the time delay of ± Δt to probe STDP responses.

Figure 6

(a) Pulsing scheme to demonstrate the excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) response based potentiation (P) and depression (D) of synaptic weight by applying 500 consecutive write (W) pulses (− 2.5 V, 10 ms) and erase (E) pulses (+ 2.5 V, 10 ms), respectively. A read pulse (− 2.0 V, 10 ms) is used to record synaptic weight change after every set of W/E pulses. (b) Potentiation and depression curve of synaptic weight change. Insets illustrate enlarged marked areas to visualize discrete conducting states during potentiation and depression. (c) Schematic of a single layer neural network used for MNIST pattern recognition. (d) Selected weight evolution mapping images from the output neurons layer corresponding to class “3” at different epochs starting from 0 to 499. (e) Training accuracy (%) vs number of epochs for both software and actual synaptic device based weight distribution. (d) Test accuracy (%) variation with the number or strength of device weight levels.