Towards in vivo neural decoding

Abstract

Conventional spike sorting and motor intention decoding algorithms are mostly implemented on an external computing device, such as a personal computer. The innovation of high-resolution and high-density electrodes to record the brain's activity at the single neuron level may eliminate the need for spike sorting altogether while potentially enabling in vivo neural decoding. This article explores the feasibility and efficient realization of in vivo decoding, with and without spike sorting. The efficiency of neural network-based models for reliable motor decoding is presented and the performance of candidate neural decoding schemes on sorted single-unit activity and unsorted multi-unit activity are evaluated. A programmable processor with a custom instruction set architecture, for the first time to the best of our knowledge, is designed and implemented for executing neural network operations in a standard 180-nm CMOS process. The processor's layout is estimated to occupy 49 mm ${}^2$ of silicon area and to dissipate 12 mW of power from a 1.8 V supply, which is within the tissue-safe operation of the brain.

Keywords: Application-specific integrated circuits; Brain-machine interfaces; Neural decoding.

Fig. 1

a Neuron rate coding and b ensemble rate coding

Fig. 2

The training and validation loss for neuron rate coding and ensemble rate coding over various training epochs

Fig. 3

The in vivo neural decoding paradigms

Fig. 4

a The block diagram of a TCN layer and b the TCN-based decoder

Fig. 5

a The training performance and b the $R^2$ score of the TCN-based decoder for both decoding paradigms

Fig. 6

The system-level diagrams of a conventional and b the fully-implantable wireless BMIs

Fig. 7

The top-level block diagram of the designed and implemented neural network processor

Fig. 8

The program snippet for computing the dilated convolution

Fig. 9

The ASIC layout of the designed and implemented neural network processor