Low-voltage self-assembled indium tin oxide thin-film transistors gated by microporous SiO2 treated by H3PO4

Abstract

Ultralow-voltage (0.8 V) thin-film transistors (TFTs) using self-assembled indium-tin-oxide (ITO) as the semiconducting layer and microporous SiO₂ immersed in 5% H₃PO₄ for 30 minutes with huge electric-double-layer (EDL) capacitance as the gate dielectric are fabricated at room temperature. The huge EDL specific capacitance is 8.2 μF cm^-2 at 20 Hz, and about 0.7 μF cm^-2 even at 1 MHz. Both enhancement mode (V _th = 0.15 V) and depletion mode (V _th = -0.26 V) operation are realized by controlling the thickness of the self-assembled ITO semiconducting layer. Electrical characteristics with the equivalent field-effect mobility of 65.4 cm² V^-1 s^-1, current on/off ratio of 2 × 10⁶, and subthreshold swing of 80 mV per decade are demonstrated, which are promising for fast-switching and low-power electronics on temperature-sensitive substrates.

Fig. 1. Fabrication of self-assembly ITO TFTs gated by solution-processed microporous SiO₂ on glass substrates.

Fig. 2. (a) Schematic diagram of EDL formation of the ITO-TFTs gated by solution-processed microporous SiO₂ dielectric. (b) The C–f characteristics for solution-processed microporous SiO₂ and common SiO₂, respectively. Inset: cross-section SEM image of such SiO₂ dielectric.

Fig. 3. (a) Frequency dependence of the ionic conductivity for the solution-processed microporous SiO₂. (b) The drain current response to a square wave pulse gate voltage for 0.05 Hz.

Fig. 4. (a) The transfer curves and (b) output characteristics of the TFTs with 40 nm ITO channel. (c) The transfer curves and (d) output characteristics of the TFTs with 10 nm ITO channel.