Highly Integrated Multiplexing and Buffering Electronics for Large Aperture Ultrasonic Arrays

Abstract

Large aperture ultrasonic arrays can be implemented by tiling together multiple pretested modules of high-density acoustic arrays with closely integrated multiplexing and buffering electronics to form a larger aperture with high yield. These modular arrays can be used to implement large 1.75D array apertures capable of focusing in elevation for uniform slice thickness along the axial direction which can improve image contrast. An important goal for large array tiling is obtaining high yield and sensitivity while reducing extraneous image artifacts. We have been developing tileable acoustic-electric modules for the implementation of large array apertures utilizing Application Specific Integrated Circuits (ASICs) implemented using 0.35 μ m high voltage (50 V) CMOS. Multiple generations of ASICs have been designed and tested. The ASICs were integrated with high-density transducer arrays for acoustic testing and imaging. The modules were further interfaced to a Verasonics Vantage imaging system and were used to image industry standard ultrasound phantoms. The first-generation modules comprise ASICs with both multiplexing and buffering electronics on-chip and have demonstrated a switching artifact which was visible in the images. A second-generation ASIC design incorporates low switching injection circuits which effectively mitigate the artifacts observed with the first-generation devices. Here, we present the architecture of the two ASIC designs and module types as well imaging results that demonstrate reduction in switching artifacts for the second-generation devices.

Figure 1

Illustration of a large aperture ultrasonic array which has benefits for imaging of deep lesions for cancer diagnosis and screening. These include improved contrast due to electronic focus in elevation and improved lateral resolution due to a reduced F#.

Figure 2

Illustration of different multiplexing and buffering architectures and parasitic effects. (a) First-generation ASICs with a single buffer and high voltage select switch (red); each buffer has a high voltage transmit/receive switch (not shown) that effectively makes this path bidirectional, (b) single-unit cell, (c) second-generation ASIC modules with single buffers (and T/R switch, not shown) off-chip at top of each column, (d) effects of parasitics when multiple ASICs with on-chip buffers are ganged together, and (e) multiple ASICs with off-chip buffers.

Figure 3

The first- (a, b) and second- (c, d) generation ASICs incorporating multiple mux switches for interfacing to 2D and 1.75D transducer array elements. (a) First-generation ASIC unit cell, (b) complete first-generation device, (c) complete second-generatation ASIC, (d) second-generation ASIC unit cell CAD layout ((b) adapted from [30], (c-d) adapted from [40]).

Figure 4

Schematic representation of the ASIC unit cells. (a) First-generation with integrated buffer, illustrating the transmit/receive protection high voltage switches (TX, RX1, and RX2) as well as the matrix multiplexing switch (SEL), and digital data storage D flip-flop connected to DIN, (b) small signal circuit model for (a), (c) second-generation ASIC unit cell without buffer and transmit/receiving circuit, (d) small-signal circuit model for (c), operation of the unit cell of (a) when (e) deselected, (f) selected in transmit mode, and (g) selected in receive mode. The red arrows show the transmit signal path, while the green arrows show the receive signal path.

Figure 5

Timing diagram for operation of the unit cell circuitry of Figure 4. The circuit operates in separate TX and RX states, with the TX switch being enabled during the TX state and the two RX switches being enabled during the RX state. This effectively serves to route high voltage signals around the amplifier while also removing the low impedance feedback path of the TX switch during the RX state.

Figure 6

ASIC unit cell layouts: (a) first-generation device and (b) second-generation device.

Figure 7

Switch architecture for the first- and second-generation switches. All switches used in each respective unit cell (e.g., select and transmit/receive) utilize these basic architectures. The second-generation switches have source resistors R1 and R2 which reduce the current in the mirrors and thereby slow down charging of the switch device gate capacitances (M1/M2) to limit charge-injection. (b) adapted from [31].

Figure 8

Simulation results for the unit switch. The switch operates in DYNAMIC and STATIC modes: In the STATIC precharge mode, the gates of M1/M2 are charged to a low voltage to turn them ON. Then, in the DYNAMIC mode, the gates float which allow the switch to conserve power and enables high voltage signals to pass through the devices M1 and M2 without damaging their sensitive low voltage gates.

Figure 9

Receive frequency response of the unit cells, (a) model (Equation (1)) comparison of first-generation response when loaded with ultrasound cable (100 pF case) vs. unloaded (10 pF case) as with a PCB connection, and (b) plots of the models of Equation (1) and Equation (2) as compared to actual measured data with the first- and second-generation ASIC modules utilizing a 16 pF series capacitance and function generator as a source load model of the transducers in receive mode.

Figure 10

Integration of first- and second-generation ASICs with respective acoustic stacks. (a) first-generation module, (b) second-generation module including MAX4805 receive buffers ((a) adapted from [30] (b) from [31]).

Figure 11

Validation of electrical function of the first-generation ASICs. (a) receive test and (b) high voltage switch test.

Figure 12

The parasitic capacitances at the inputs of the first- and second-generation modules were determined using the circuits in (a) for first- and (b) for second-generation devices. The table in (c) shows calculated values for first- and second-generation with increasing $N$. The final value for Cpn was calculated as the mean of the 4 measured values.

Figure 13

Transmit ON resistance of the individual ASIC module channels was measured as illustrated in (a) for the first-generation architecture and (b) for the second-generation device. The attenuation, α, is visible in (c) where the red trace is the input signal and the purple trace is the attenuated voltage measured across ${\text{R}}_{\text{Test}}$. Calculated ${\text{R}}_{\text{Transmit}}$ values for first- and second-generation are tabulated in (d).

Figure 14

The transmit off-isolation was measured by operating the first- and second-generation modules interfaced to the Verasonics system with a single cycle pulse at 38 Vpp and $\text{Fc}=3.5\text{MHz}$. (a) shows the result when the switch is ON, and (b) shows the result when the switch is OFF. As can be seen in (b), the transmitted pulse is effectively reduced by 46 dB with the switch turned off, and (c) tabulates these results.

Figure 15

Measurement of Glitch level. (a) Verasonics receive signal with arrow indicating the glitch echo, (d) analogous voltage oscilloscope trace measurement, with arrow indicating observed outgoing glitch waveform (pink trace) in response to digital control signal (green trace) that turns on the switch. Translating control signal (e) moves the glitch response (arrow in (b)). (c) When transmit pulses are turned off, the acoustic response prior to the glitch disappears; however, the glitch itself is unchanged indicating that it is caused by switching transients.

Figure 16

Acoustic imaging tests for the (a) first- and (b) second-generation acoustic/ASIC modules imaging a highly echogenic cyst and a vertical group of wires in a CIRS 054GS ultrasound phantom. Displayed dynamic range for the images was 40 dB.

Figure 17

Glitch reduction in second-generation devices when imaging quartz target, (a) first-generation ASIC module (b) second generation ASIC module, arrows show the location of the image artifact due to glitches (c-d) show plots of the Verasonics RF receive data for (c) the first-generation and (d) the second generation ASIC mdoules, arrows indicate where the glitches are located. (adapted from [31]).