Planar Junctionless Field-Effect Transistor for Detecting Biomolecular Interactions

Abstract

Label-free field-effect transistor-based immunosensors are promising candidates for proteomics and peptidomics-based diagnostics and therapeutics due to their high multiplexing capability, fast response time, and ability to increase the sensor sensitivity due to the short length of peptides. In this work, planar junctionless field-effect transistor sensors (FETs) were fabricated and characterized for pH sensing. The device with SiO₂ gate oxide has shown voltage sensitivity of 41.8 ± 1.4, 39.9 ± 1.4, 39.0 ± 1.1, and 37.6 ± 1.0 mV/pH for constant drain currents of 5, 10, 20, and 50 nA, respectively, with a drain to source voltage of 0.05 V. The drift analysis shows a stability over time of -18 nA/h (pH 7.75), -3.5 nA/h (pH 6.84), -0.5 nA/h (pH 4.91), 0.5 nA/h (pH 3.43), corresponding to a pH drift of -0.45, -0.09, -0.01, and 0.01 per h. Theoretical modeling and simulation resulted in a mean value of the surface states of 3.8 × 10¹⁵/cm² with a standard deviation of 3.6 × 10¹⁵/cm². We have experimentally verified the number of surface sites due to APTES, peptide, and protein immobilization, which is in line with the theoretical calculations for FETs to be used for detecting peptide-protein interactions for future applications.

Keywords: diagnostics; pH sensor; peptide-protein interaction; peptidomics; planar junctionless FETs; proteomics; therapeutics.

Figure 1

(A) Schematic of the proposed planar junctionless FETs and (B) cross-sectional view of the proposed device design.

Figure 2

Fabrication process flow of the planar junctionless FETs. (i) cleaning SOI wafer, (ii) thinning of device layer using oxidation and etching, (iii) silicon dioxide growth as a masking layer, (iv) patterning silicon dioxide and boron diffusion, (v) etching silicon dioxide, (vi) silicon nitride deposition, (vii) patterning silicon nitride to define silicon islands, (viii) etching silicon nitride, (ix) gate oxide growth, (x) patterning gate oxide to define source and drain regions, (xi) Ta/Pt Metal lift-off, (xii) patterning SU-8 passivation layer, and (xiii) patterning SU-8 channels.

Figure 3

Fabricated chip design and encapsulation. (A) image of the single chip, (B) SU-8 channels, (C) gate opening of a single FET in a thin SU-8 layer. Color change is observed at doped source and drain regions due to the formation of a PtSi alloy, and (D) encapsulation with epoxy glue.

Figure 4

I-V characteristics at fixed pH of 4.91 (A) I_ds vs. V_ds for a varying gate voltage, applied via the reference electrode (−0.1 to −0.5 V in steps of −0.1 V) with V_ds ranging from −0.05 V to 0.05 V, and (B) I_ds vs. V_gs for input gate voltage range of −1 to 1 V, applied via the reference electrode for a V_ds of 0.05 and 0.1 V. Voltage and current sensitivity analysis (C) V_gs vs. pH, and (D) average I_ds vs. pH.

Figure 5

Simulation and modeling of the junctionless FETs. (A) Scheme for the surface sites available in SiO₂. (B) Calibration of the simulated model with the experimental data in terms of reference gate bias with respect to the electrolyte pH. Separated graphs for different current values of 5 nA, 10 nA, 20 nA, and 50 nA while representing the possible RMSE error using surface states as the fitting parameter. The used color codes are the same for corresponding current values.

Figure 6

Drift characterization. (A) Current vs time step response for different pH and (B) current vs. time for a longer time for several constant pH values.