Two dimensional semiconducting materials for ultimately scaled transistors

Abstract

Two dimensional (2D) semiconductors have been established as promising candidates to break through the short channel effect that existed in Si metal-oxide-semiconductor field-effect-transistor (MOSFET), owing to their unique atomically layered structure and dangling-bond-free surface. The last decade has witnessed the significant progress in the size scaling of 2D transistors by various approaches, in which the physical gate length of the transistors has shrank from micrometer to sub-one nanometer with superior performance, illustrating their potential as a replacement technology for Si MOSFETs. Here, we review state-of-the-art techniques to achieve ultra-scaled 2D transistors with novel configurations through the scaling of channel, gate, and contact length. We provide comprehensive views of the merits and drawbacks of the ultra-scaled 2D transistors by summarizing the relevant fabrication processes with the corresponding critical parameters achieved. Finally, we identify the key opportunities and challenges for integrating ultra-scaled 2D transistors in the next-generation heterogeneous circuitry.

Keywords: Devices; Electrical engineering; Nanomaterials.

Graphical abstract

Figure 1

The evolution trend of the technology nodes for Si transistors The Cu BEOL image is reproduced with permission from (Miller, 1999) Copyright© 1999, American Association for the Advancement of Science. The stacked 2D device-based inverter is reproduced with permission from (Schram et al., 2022) Copyright© 2022 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Figure 2

Short channel effects for Si and 2D transistors (A) Schematic illustration of the Si transistor at the extreme scale. (B) Energy band diagram of typical transistor in long and short channel configurations. The DIBL and nature length λ are indicated for reference. (C) The crystalline structure of typical 3D bulk materials with obvious dangling bonds on the rough surface. (D) The crystalline structure of typical 2D TMD and graphene which are dangling bond free with uniform thickness even scaling down to the atomic layer. (E) Carrier mobility as a function of channel thickness for both 3D Si (Schmidt et al., 2009; Uchida et al., 2002), Ge (Yu et al., 2015), and typical 2D semiconductors including MoS₂ (Cui et al., 2015; Lembke et al., 2015; Li et al., 2019; Liu et al., 2016a; Shen et al., 2021; Xie et al., 2017; Yu et al., 2016), WS₂ (Alharbi et al., 2017; Ovchinnikov et al., 2014), WSe₂ (Allain and Kis, 2014; Fang et al., 2012; Liu et al., 2013), MoTe₂ (Zhang et al., 2019a). The carrier mobility degrades rapidly in the empirical relationship of μ∼t⁻⁶ for 3D bulk transistors, while the mobility can still maintain above 100 cm V⁻¹·s⁻¹ for 2D transistors.

Figure 3

A summary of ultra-scaled 2D transistors achieved through shrinking the channel and gate length, respectively

Figure 4

Channel length scaling of 2D transistors based on EBL technology (A) Schematic of monolayer MoS₂ transistor using semimetal Bicontacts. (B) Band alignment between semimetal and semiconductor. The metal-induced gap sates (MIGS) in semiconductor are saturated when contacting with semimetal, leading to the negligible Schottky barrier height as well as low contact resistance. (C) Output curves of short channel MoS₂ transistor measuring at different gates from −10 V to 30 V. The maximum I_on can be as high as 1135 μA μm⁻¹; Inset shows the SEM image of the as-fabricated device. (D) Projected I_ON as a function channel length for monolayer TMDs transistors using different contact technologies. Figures A, B, C, and D are reproduced with permission from (Shen et al., 2021) Copyright© 2021, Springer Nature. (E) Schematic illustration of the hybrid ML PTCDA/HfO₂ gate stack on 2D materials. Inset: a 10 nm × 10 nm high-resolution STM scan of ML PTCDA on graphene. (F) Transfer characteristics of the short channel ML MoS₂ transistor using ultrathin PTCDA/HfO₂ gate dielectric. Inset shows the corresponding SEM image of the transistor. Figures E and F are reproduced with permission from (Li et al., 2019) Copyright© 2019, Springer Nature. (G) Schematic of the two-step EBL fabrication process for achieving the 2D short channel transistors in sub-20 nm. (H) Transfer characteristics of the ML MoS₂ transistor fabricated by the two-step EBL process; Inset shows the SEM image of the transistor with a channel length of 14 nm. (I) Current on/off ratio as a function of V_DS with a channel length of 14 and 50 nm, respectively. Figures G, H, and I are reproduced with permission from (Zhu et al., 2018) Copyright© 2018, American Chemical Society.

Figure 5

Channel length scaling of 2D transistors with nanogap (A) Upper: schematic diagram of nanogaps achieved by suspended SWCNT masks; Below: SEM image of the corresponding nanogaps in 7.5 nm. Reproduced with permission from (Xiao et al., 2019) Copyright© 2019, American Chemical Society. (B) Upper: Schematic diagram of nanogaps on Bi₂O₃ substrate via HNO₃ etching. Below: the as-fabricated short channel MoS₂ transistor in top-gate configuration. (C) Transfer characteristics of the MoS₂ transistor with channel length of 8.2 nm. (D) Output characteristics of the inverter based on 2D short-channel transistors. Figures B, C, and D are reproduced with permission from (Xu et al., 2017) Copyright© 2017, American Chemical Society. (E) Schematic image of the short-channel device fabricated by transferring 2D flakes on top of utraflat template-stripped metal electrodes with nanoscale gap. (F) AFM image of MoS₂ flake on Au surface with a nanogap. Figures E and F are reproduced with permission from (Namgung et al., 2021) Copyright© 2021, American Chemical Society. (G) Schematic illustration of graphene-contacted ultra-short channel MoS₂ transistors in top-gated geometry. (H) Transfer characteristics of the 4 nm top-gated MoS₂ transistors at different bias voltages from 20 to 100 mV. Inset shows the corresponding AFM image. (I) Channel length-dependent current on/off ratio, mobilities, SS, and DIBL of back-gated MoS₂ transistors. Figure G, H, I are reproduced with permission from (Xie et al., 2017) Copyright© 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Figure 6

Channel length scaling based on vertical device configuration (A) Schematic illustration of the 2D vertical FET with mainly six layers which are the bottom electrode, insulating spacer, top electrode, 2D vertical channel, top-side gate insulator, and gate electrode. (B) Transfer characteristics of the 2D vertical FET and conventional 2D planar FET. Inset: schematic illustration of the local enhancement of electric field in 2D vertical FET. Figures A and B are reproduced with permission from (Jiang et al., 2020) Copyright© 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (C) Cross-sectional schematic of 2D vertical FET fabricated by using vdW electrodes. The items from bottom to top are graphene, MoS₂, and vdW electrode, respectively. (D) 2D plot of I_ds versus temperature (y axis) and gate voltage (x axis) for the device with vdW electrode. The bias voltage is fixed at 0.5 mV. Figures C and D are reproduced with permission from (Liu et al., 2021b) Copyright© 2021, Springer Nature. (E) Schematic diagram of the 2D vertical FET based on SWCNT network and MoS₂ heterostructure. (F) Electrostatic screening effect simulation of the gate electric field in the SWCNT network/MoS₂ heterostructure. The red arrows indicate the electric field from the Si gate through the SWCNT electrode, MoS₂ channel, to the Au metal electrode. Figures E and F are reproduced with permission from (Phan et al., 2019) Copyright© 2019, American Chemical Society.

Figure 7

2D MBCFETs (A) Schematic structure of MBCFET with two-level-stacked channels. (B) High-resolution TEM and EDS mapping of the MBC FET. (C) On-state and off-state current of 2D ultrathin MBCFET dependent on the VD voltage bias. Figures A, B, and C are reproduced with permission from (Huang et al., 2021a) Copyright© 2021 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (D) Structure schematic of the 2-stacked MoS₂ nanosheets device. The ALD-grown HfO₂ is used as the dielectric layer in the device. (E) Transfer characteristics of the short channel MoS₂ MBC FET with L_ch of 160 nm. Inset shows the corresponding SEM image displaying the L_g and L_ch. Figures D and E are reproduced with permission from (Xiong et al., 2021) Copyright© 2021, IEEE. (F) One-step 2D-channel formation on suspended bridges. Reproduced with permission from (Liu et al., 2021a) Copyright© 2021 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Figure 8

Gate length scaling through integrating one-dimensional CNT/nanowire (A) Cross-sectional TEM image of the bilayer MoS₂ transistor with 1-nm gate length, where SWCNT and ZrO₂ are used as the gate electrode and dielectric layer, respectively. (B) Transfer characteristics and the corresponding leakage current of the SWCNT gated MoS₂ transistor at V_DS = 50 mV and 1 V. (C) Electric field contour plots for a simulated bilayer MoS₂ device in the Off and On states. Figures A, B, and C are reproduced with permission from (Desai et al., 2016) Copyright© 2016, American Association for the Advancement of Science. (D) Cross-sectional TEM image of monolayer MoS₂ FET gated by 1D metallic Co₂Si nanowire. (E) The relationship between channel length L_ch and Co₂Si nanowire radius r for MoS₂ transistors in ultra-scaled gate length. Inset shows a simplified circular-shaped Co₂Si nanowire. Figures D and E are reproduced with permission from (Cao et al., 2016) Copyright© 2016, IEEE. (F) Schematic of monolayer MoS₂ in side-wall gate configuration by using monolayer graphene edge gate with a thickness of 0.34 nm. (G) Optical image of the 0.34 nm L_g side-wall transistor arrays on a 2-inch wafer. (H) The timescale evolution of gate length in ultra-scaled 2D transistors. Figures F, G, and H are reproduced with permission from (Ren et al., 2020) Copyright© 2020, Springer Nature.

Figure 9

2D FinFETs (A) Cross sectional TEM image of MoS₂ FinFET using Si back gate. (B) Transfer characteristics of the MoS₂ FinFET with 4 nm thin body sweeping by the front gate voltage. Inset shows the SEM image of the device for measurement. (C) The development trends of the FinFET channel thickness and gate length. Figures A, B, and C are reproduced with permission from (Chen et al., 2015) Copyright© 2015, IEEE. (D) Left: The simulated field effect curves of 4 nm gate length FinFET. Right: Statistics of on/off ratio and mobility of MoS₂ ML-FinFET. (E) Schematic illustration of the 2D FinFET with W_fin of 0.6 nm. The monolayer MoS₂ crystal is grown over a 300 nm height Si step with the side wall coated by HfO₂ dielectric. (F) A timescale evolution of W_fin for the transistors in FinFET configuration. Figures D, E, and F are reproduced with permission from (Chen et al., 2020) Copyright© 2020, Springer Nature.

Figure 10

2D transistors achieved via self-aligned engineering technique (A) Cross-sectional TEM image of the 2D MoS₂ SATFET with L_g of 10 nm in false color. (B) Transmission (Tr) vs V_DS for the 2D SATFET under gate length of 10 nm at a temperature of 225 K. Inset shows conduction band diagram for the carrier transport cross the barrier. (C) Tr and effective velocity (v_EFF) as a function of temperature. Figures A, B, and C are reproduced with permission from (English et al., 2016) Copyright© 2016, IEEE. (D) Optical images of the Bicontacted MoS₂ SATFETs in arrays over 6 mm². The corresponding false-colored SEM image of a single top-gated SATFET is also demonstrated at the bottom right. (E) Benchmark of R_C versus I_ON of the top-gated monolayer CVD MoS₂ FETs. (F) Benchmark of on/off ratio versus I_ON. Figures D, E, and F are reproduced with permission from (Li et al., 2021) Copyright© 2021, IEEE. (G) Schematic of the self-aligned GaN nanowire top-gated MoS₂ FETs. (H) Output characteristics of the self-aligned MoS₂ transistor under different strains without applying gate voltage. Inset shows the schematics of the effects of strain on the transistor. Gradient ramp indicates the piezo-potential in GaN NW; red and blue indicate positive and negative piezo-potential, respectively. Figures G, H are reproduced with permission from (Liu et al., 2016a) Copyright© 2016, American Chemical Society.

Figure 11

Contact scaling based on edge contact technique (A) Schematic of 2D FET with traditional top contacts and edge contacts. (B) Relationship between I_d and L_c for in-situ edge contacts after aligning V_th, showing potential for sustaining performance while scaling contact length. Reproduced with permission from (Cheng et al., 2019) Copyright© 2019, American Chemical Society. (C) The transfer curve of the monolayer MoS₂ transistor with edge contacts. Inset shows the corresponding schematic of the device for measurement. Reproduced with permission from (Jain et al., 2019) Copyright© 2019, American Chemical Society. (D) SEM image of the hetero-phase MoS₂ transistor with L_ch = 7.5 nm. (E) MIT Virtual Source Compact modeling (MVS) of the transfer curve of the hetero-phase MoS₂ short channel transistor. Inset shows circuit configuration consisting of a chain of six MoS₂ FETs used in the MVS model. Figures D and E are reproduced with permission from (Nourbakhsh et al., 2016) Copyright© 2016, American Chemical Society. (F) Transfer curve of CNT-gated p-type MoTe₂ FET in 1T′-2H hetero-phase configuration. Inset shows the corresponding schematic of the device for measurement. Reproduced with permission from (Zhang et al., 2019a) Copyright© 2019, Springer Nature.