On the Role of Speed in Technological and Biological Information Transfer for Computations

Abstract

In all kinds of implementations of computing, whether technological or biological, some material carrier for the information exists, so in real-world implementations, the propagation speed of information cannot exceed the speed of its carrier. Because of this limitation, one must also consider the transfer time between computing units for any implementation. We need a different mathematical method to consider this limitation: classic mathematics can only describe infinitely fast and small computing system implementations. The difference between mathematical handling methods leads to different descriptions of the computing features of the systems. The proposed handling also explains why biological implementations can have lifelong learning and technological ones cannot. Our conclusion about learning matches published experimental evidence, both in biological and technological computing.

Keywords: Biological computing; Computing paradigm; Information storage; Information transfer speed; Lifelong learning; Machine learning; Redundancy; Technological computing; Temporal behavior.

Fig. 1

The temporal diagram, i.e., the way of calculation to combine the spatial distance (transmission time, blue arrows) and computing time (green arrows) illustrated in the time-space coordinate system. The orange-green vertical arrow shows that the second computing unit must idly wait until the transmitted result reaches its position, because of the finite transmission time. The axes x and y refer to space coordinates (transformed to time using the conduction velocity), the axis t refers to the time itself. The arrows starting from points 0, 1 and 2 on the x axis illustrate timing for three different propagation speeds. The red vector points from the beginning to the end of the process. Its length may serve as a statistical entity to describe temporal distance of the units. (Color figure online)

Fig. 2

The operation of a technological one-bit adder, with "pointless" synchronization (red circles), see Listing 1. The input signals a, b and $c_i$ are aligned along axis y (the input section), the computation takes part in gates aligned along axis x, and the output signals $c_o$ and sum aligned again along axis y (the output section). The figure uses the coordinate system introduced in Fig. 1

Fig. 3

The history of different relative dispersion characteristics of processors, in function of their production year. Notice how cramming more transistors in a processor changed their temporal characteristics disadvantageously. The technological data are calculated from publicly available data (https://en.wikipedia.org/wiki/Transistor_count) and from Eckert and Mauchly (1945), as described in Végh (2021)

Fig. 4

How neurons learn. A The initial state B short time learning, changing synaptic weight $W_3$ by +50% c long time learning, changing conduction velocity $C_3$ by +10%. The figure uses the coordinate system introduced in Fig. 1. The figure shows a neuronal assembly, where the assembly member $A_3$ changes the timing of Target due to changing the synaptic weight $W_3$ and conduction velocity $C_3$, respectively

Fig. 5

The temporal operating diagram of a technological high-speed single bus: the bus delivers data only in the fractions denoted by vertical green arrows. In most of the time the ‘neurons’ are contending for the right to use the single high-speed bus. (Color figure online)

Fig. 6

The temporal operating diagram of a parallelized sequential (distributed) computing system: one processor coordinates the work of fellow processors, causing an inherent efficiency bound

Fig. 7

The temporal behavior of the technological components results in that the payload efficiency of vast computing systems sharply decreases as the number of processors increases; the architecture defines the parallelization efficiency. Notice the reasoned guess for the efficacy of simulating the brain, resulting from the vast numbers of computing units and the disruptive workload