Fabrication methods for high reflectance dielectric-metal point contact rear mirror for optoelectronic devices

Abstract

The patterned dielectric back contact (PDBC) structure can be used to form a point-contact architecture that features a dielectric spacer with spatially distributed, reduced-area metal point contacts between the semiconductor back not recognized contact layer and the metal back contact. In this structure, the dielectric-metal region provides higher reflectance and is electrically insulating. Reduced-area metal point contacts provide electrical conduction for the back contact but typically have lower reflectance. The fabrication methods discussed in this article were developed for thermophotovoltaic cells, but they apply to any III-V optoelectronic device requiring the use of a conductive and highly reflective back contact. Patterned dielectric back contacts may be used for enhanced sub-bandgap reflectance, for enhanced photon recycling near the bandgap energy, or both depending on the optoelectronic application. The following fabrication methods are discussed in the article•PDBC fabrication procedures for spin-on dielectrics and commonly evaporated dielectrics to form the spacer layer.•Methods to selectively etch a parasitically absorbing back contact layer using metal point contacts as an etch mask.•Methods incorporating a dielectric etch through different process techniques such as reactive ion and wet etching.

Keywords: Dielectrics; High-reflectivity mirror; Optoelectronics; Photovoltaics; SU-8; Via contacts.

Graphical abstract

Fig. 1

(a) Plan-view schematic of the patterned dielectric back contact layer. Yellow discs are the spatially distributed point contacts, and the blue region is the dielectric spacer. Figures illustrating III-V optoelectronic devices with (b) III-V BCL intact; and (c) III-V BCL selectively etched patterned dielectric back contacts are shown.

Fig. 2

Classification of PDBC fabrication processes.

Fig. 3

Schematic of PDBC fabrication process flow A, used primarily for SU-8 photoresist as the dielectric layer. Process A1 for SU-8 first process (a) A1-RIE – thickness control through RIE; (b) A1-spin – thickness control through SU-8 dilution; and (c) process A2 for metal point contact first process; for a structure in which the back contact layer is etched everywhere except at the point contacts; and shows the two different sub-processes A2-no mask and A2-with mask in steps 5, 6.

Fig. 4

(a) Etched SU-8 thickness as a function of RIE-ICP etch time in RF power 50 W, ICP power 300 W, 50 sccm O₂ flow, 10 mT chamber pressure in O₂ plasma with He backed substrate cooling at 10 torr (b) Mean, and RMS surface roughness measured using AFM (c) SU-8 thickness as a function of SU-8 concentration diluted in CPG thinner, spin-coated at 6000 RPM after hardbake at 100°C for 30 mins. Dashed lines in the figures indicate linear fits to the data.

Fig. 5

Schematic of PDBC fabrication process flow B primarily for evaporable dielectrics: (a) process B1 for etchable dielectrics and no support for BCL etch; and (b) process B2 for any dielectrics that supports BCL etch.