A Conductance-Based Silicon Synapse Circuit

Abstract

Neuron, synapse, and learning circuits inspired by the brain comprise the key components of a neuromorphic chip. In this study, we present a conductance-based analog silicon synapse circuit suitable for the implementation of reduced or multi-compartment neuron models. Compartmental models are more bio-realistic. They are implemented in neuromorphic chips aiming to mimic the electrical activities of the neuronal networks in the brain and incorporate biomimetic soma and synapse circuits. Most contemporary low-power analog synapse circuits implement bioinspired "current-based" synaptic models suited for the implementation of single-compartment point neuron models. They emulate the exponential decay profile of the synaptic current, but ignore the effect of the postsynaptic membrane potential on the synaptic current. This dependence is necessary to emulate shunting inhibition, which is thought to play important roles in information processing in the brain. The proposed circuit uses an oscillator-based resistor-type element at its output stage to incorporate this effect. This circuit is used to demonstrate the shunting inhibition phenomenon. Next, to demonstrate that the oscillatory nature of the induced synaptic current has no unforeseen effects, the synapse circuit is employed in a spatiotemporal spike pattern detection task. The task employs the adaptive spike-timing-dependent plasticity (STDP) learning rule, a bio-inspired learning rule introduced in a previous study. The mixed-signal chip is designed in a Taiwan Manufacturing Semiconductor Company 250 nm complementary metal oxide semiconductor technology node. It comprises a biomimetic soma circuit and 256 synapse circuits, along with their learning circuitries.

Keywords: adaptive STDP; biomimetic synapse circuit; neuromorphic computing; shunting inhibition; spike pattern detection; synaptic resolution; synaptic reversal potential.

Figure 1

A schematic illustration of a neuronal cell with excitatory and shunting inhibitory synapses. The EPSP generated by excitatory synapse attenuates as it reaches the soma.

Figure 2

(A) Conductance-based synapse circuit with an oscillator-based transconductance stage. (B) Output stage of current-based excitatory and inhibitory synapse circuit with the same digital-to-analog converter (DAC) and integrator as the first two stages.

Figure 3

Transient of the oscillator’s frequency in a typical synaptic event. The circuit activates at 50 ms with $s{V}_{\mathrm{t}}$ = 100 mV, $s{V}_{\mathrm{w}}$ = 280 mV, and maximum synaptic efficacy. (A) Frequency plot of the oscillator’s output; (B) natural logarithm of the frequency plot in (A); (C) the slope of the plot in (B). Plots (B) and (C) show that the oscillator’s frequency decays exponentially in a typical synaptic event. The exponential dependence is lost when M11 comes out of the saturation region (V_syn < 4 U_T).

Figure 4

The synapse circuit is activated at 50 ms with $s{V}_{\mathrm{t}}$ = 100 mV, $s{V}_{\mathrm{w}}$ = 280 mV, and maximum synaptic efficacy. (A) Linearly discharging profile of V_syn; (B) profile of V_{in_osc}. Oscillations are owing to the current sourced out of the oscillator circuit; (C) moving average profile of the node V_{in_osc}, plotted with a time window of 15 ms; (D) profile of the node V_{out_osc} showing oscillator’s output, where the amplitude of the oscillations decreases linearly; (E) the induced synaptic current plotted with a time window of 5 ms.

Figure 5

Block diagram representation of the neuron’s architecture. The current conveyor as a link implements a single-compartment point neuron model. It also fixes the voltage at node V_post equal to V_{CC_ref}. The unidirectional resistor R_c as a link implements the unidirectional two-compartment model.

Figure 6

(A) Unidirectional resistor designed using a single-stage source degenerated transconductance circuit; (B) current conveyor circuit with two output branches. I_out (I_{out_rev}) is used when the 256 synapse circuits are connected to V_post via terminal I_{syn_exc} (I_syn).

Figure 7

Adaptive spike-timing-dependent plasticity (STDP) learning. (A) Rectangular STDP learning rule; (B) adaptation of t_post in rectangular STDP learning rule during the learning process.

Figure 8

Learning circuitry. (A) Block diagram; (B) Long term potentiation (LTP) half-circuit.

Figure 9

(A) Synaptic current measured as voltage for 21 different values of $E_{\mathrm{syn}}$ (500 mV to 700 mV) with $V_{\mathrm{mem}}$ = 600 mV. Each of the 21 measurements were repeated six times and ignorable standard deviation was observed among the repeated runs; (B) non-linear I–V relationship. The Orange trace plots the peak intensities of synaptic currents in (A) and the purple trace plots the same with $V_{\mathrm{dd}\_\mathrm{osc}}$ and $s{V}_{\mathrm{w}}$ reduced to 500 mV and 340 mV, respectively. Both traces are plotted against corresponding values of $E_{\mathrm{syn}}$.

Figure 10

Demonstration of shunting inhibition. (A) Three traces of dendritic membrane potentials corresponding to Runs 1, 2, and 3, respectively. Each trace was measured ten times. The figure shows the moving average data of three single traces plotted with a time window of 50 µs. Depolarization reduces when both excitatory and shunting inhibitory synapse circuits are activated together; (B) somatic and dendritic membrane potentials for two different runs. Synchronous activation of four synapse circuits causes the soma to spike (blue trace). However, if the additional shunting inhibitory synapse circuit is simultaneously activated, the depolarization is not strong enough and the soma does not spike (green trace).

Figure 11

(A) Membrane potential of the soma circuit during the run; (B) soma circuit’s membrane potential during the last second; it spikes within the shaded 50 ms spike pattern; (C) the adaptation of VLTD during learning; (D) bimodal distribution of synaptic efficacies after learning.