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Review
. 2022 Dec 19;12(24):4488.
doi: 10.3390/nano12244488.

Ferroelectric Devices for Content-Addressable Memory

Affiliations
Review

Ferroelectric Devices for Content-Addressable Memory

Mikhail Tarkov et al. Nanomaterials (Basel). .

Abstract

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.

Keywords: FTJ; FeFET; content-addressable memory; ferroelectric; memristor.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 7
Figure 7
Energy band landscapes for different structures with different ferroelectric polarization states within the structure. (A) Metal/ferroelectric/metal (M/F/M), (B) metal/ferroelectric/interlayer/metal (M/F/IL/M), and (C) metal/ferroelectric/IL/semiconductor (M/F/IL/S) structures. The band structures are drawn using band diagram program with schematic Thomas–Fermi screening length of metals [113,114]. The interlayers of M/F/IL/M and M/F/IL/S are set as Al2O3 and SiO2, respectively. (D) Conductance ratio of FTJs, having a TiN/Hf0.5Zr0.5O2 (HZO)/ZrO2/TiN (M/F/IL/M) and TiN/HZO/ZrO2/poly-Si (M/F/IL/S) structure as a function of the pulse amplitude. (E) Retention characteristics of M/F/IL/M and M/F/IL/S FTJs; both devices were measured after wake-up field cycling of 106 cycles with ±6 V/500 ns and 10 V/500 ns for M/F/IL/M and M/F/IL/S, respectively. (F) Relative permittivity of a M/F/M capacitor as a function of the field cycles. The inset shows the device schematic (right) and a hysteresis loop of the relative permittivity (left). The relative permittivity was extracted from the small-signal capacitance measured at 0 V with a bias amplitude of 30 mV. The program/erase pulse amplitude used were 3 V/−3 V. (D,E) Reproduced with permission [104]. Copyright 2021, IEEE. (F) Reproduced with permission [115]. Copyright © 2021, IEEE [73].
Figure 1
Figure 1
CAM block diagram [18].
Figure 2
Figure 2
TCAM cell [24].
Figure 3
Figure 3
(a) FeRAM, (b) FeFET, and (c) FTJ [34].
Figure 4
Figure 4
Classic ferroelectric materials: Pb(Zr,Ti)O3, SrBi2Ta2O9, and BiFeO3 [34].
Figure 5
Figure 5
FeFET design change to improve field uniformity in ferroelectric along the channel. Copyright © 2020, IEEE [99].
Figure 6
Figure 6
Various ferroelectric devices with a three-terminal structure (upper row) and corresponding characteristics of synaptic plasticity (lower row). (A) MFIS, (B) (left) MFMIS and (right) MFMIS with the MFM capacitor integrated into the BEOL and the underlying MOSFET integrated into the FEOL, and (C) FeTFT. Schematic of FeFETs with different channel geometries and synaptic potentiation (a) or depression (b) [73].
Figure 8
Figure 8
(ac) An example of logarithmic ROFF/RON and polarization, respectively, as a function of switching voltage Copyright © 2012, 2019 American Chemical Society [122,123,124].
Figure 9
Figure 9
TCAM cell designs based on: (a) CMOS static random access memory required 16 transistors, BL, bit line, ML, pre-charged matchline, SL, search line, WL, write line, (b) based on resistive storage elements, (c) based on four CMOS FET and two FeFETs, (d) based on two FeFETs [https://arxiv.org/abs/2101.06375 Access Date: 10 December 2022].

References

    1. Horowitz M. Computing’s energy problem (and what we can do about it); Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); San Francisco, CA, USA. 9–13 February 2014; pp. 10–14.
    1. Ting T.-K.J., Wang G.-B., Wang M.-H., Wu C.-P., Wang C.-K., Lo C.-W., Tien L.-C., Yuan D.-M., Hsieh Y.-C., Lai J.-S., et al. An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache; Proceedings of the 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017; San Francisco, CA, USA. 5– February 2017; pp. 404–405.
    1. Wong H.-S.P., Lee H., Yu S., Chen Y., Wu Y., Chen P., Lee B., Chen F.T., Tsai M. Metal–oxide RRAM. Proc. IEEE. 2012;100:1951–1970. doi: 10.1109/JPROC.2012.2190369. - DOI
    1. Jeloka S., Akesh N.B., Sylvester D., Blaauw D. A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory. IEEE J. Solid-State Circuits. 2016;51:1009–1021.
    1. Do A., Yin C., Velayudhan K., Lee Z.C., Yeo K.S., Kim T.T.-H. 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. IEEE J. Solid-State Circuits. 2014;49:1487–1498. doi: 10.1109/JSSC.2014.2316241. - DOI

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