Ferroelectric Devices for Content-Addressable Memory
- PMID: 36558341
- PMCID: PMC9785747
- DOI: 10.3390/nano12244488
Ferroelectric Devices for Content-Addressable Memory
Abstract
In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.
Keywords: FTJ; FeFET; content-addressable memory; ferroelectric; memristor.
Conflict of interest statement
The authors declare no conflict of interest.
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References
-
- Horowitz M. Computing’s energy problem (and what we can do about it); Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); San Francisco, CA, USA. 9–13 February 2014; pp. 10–14.
-
- Ting T.-K.J., Wang G.-B., Wang M.-H., Wu C.-P., Wang C.-K., Lo C.-W., Tien L.-C., Yuan D.-M., Hsieh Y.-C., Lai J.-S., et al. An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache; Proceedings of the 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017; San Francisco, CA, USA. 5– February 2017; pp. 404–405.
-
- Wong H.-S.P., Lee H., Yu S., Chen Y., Wu Y., Chen P., Lee B., Chen F.T., Tsai M. Metal–oxide RRAM. Proc. IEEE. 2012;100:1951–1970. doi: 10.1109/JPROC.2012.2190369. - DOI
-
- Jeloka S., Akesh N.B., Sylvester D., Blaauw D. A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory. IEEE J. Solid-State Circuits. 2016;51:1009–1021.
-
- Do A., Yin C., Velayudhan K., Lee Z.C., Yeo K.S., Kim T.T.-H. 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. IEEE J. Solid-State Circuits. 2014;49:1487–1498. doi: 10.1109/JSSC.2014.2316241. - DOI
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