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. 2023 Jan 12;14(1):196.
doi: 10.3390/mi14010196.

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

Cosmin-Andrei Popovici  1 , Andrei Stan  1
Affiliations

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

Cosmin-Andrei Popovici et al. Micromachines (Basel). .

Abstract

Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using low-cost and reliable setups. In the context of RISC-V Extensions and Domain-Specific Architecture, this paper proposes a Real-Time RISC-V-based CAN-FD Bus Diagnosis Tool, named RiscDiag CanFd, as an open-source alternative. The RISC-V Core extension is a CAN-FD Communication Unit controlled by a dedicated ISA Extension. Besides the extended RISC-V core, the proposed SoC provides UDP Communication via Ethernet for connecting the proposed solution to a PC. Additionally, a GUI application was developed for accessing and using the hardware solution deployed in an FPGA. The proposed solution is evaluated by measuring the lost frame rate, the precision of captured frames timestamps and the latency of preparing data for Ethernet communication. Measurements revealed a 0% frame loss rate, a timestamp error under 0.001% and an acquisition cycle jitter under 10 ns.

Keywords: CAN-FD; FPGA; RISC-V; SoC; UDP; communication; ethernet; hardware acceleration.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
The Architecture of the RISC-V based CAN-FD Bus Diagnosis Tool.
Figure 2
Figure 2
RisCanFd CPU Block Diagram illustrating the CAN-FD Extension [6].
Figure 3
Figure 3
CAN-FD Bus Diagnose Module Architecture.
Figure 4
Figure 4
The Expanded Architecture of the UART Debugger.
Figure 5
Figure 5
Information Flow in the Main Application of the Driver.
Figure 6
Figure 6
The Test Setup.
Figure 7
Figure 7
Plot of recovery time measurement results from Table 5.
Figure 8
Figure 8
Oscillogram of the CAN-FD frame acquisition cycle captured with the logic analyzer.
Figure 9
Figure 9
Oscillogram presenting multiple CAN-FD acquisition cycles.
Figure 10
Figure 10
Reaction Time Comparison Chart.
See this image and copyright information in PMC

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