NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC

Abstract

Closed-loop neural interfaces with on-chip machine learning can detect and suppress disease symptoms in neurological disorders or restore lost functions in paralyzed patients. While high-density neural recording can provide rich neural activity information for accurate disease-state detection, existing systems have low channel counts and poor scalability, which could limit their therapeutic efficacy. This work presents a highly scalable and versatile closed-loop neural interface SoC that can overcome these limitations. A 256-channel time-division multiplexed (TDM) front-end with a two-step fast-settling mixed-signal DC servo loop (DSL) is proposed to record high-spatial-resolution neural activity and perform channel-selective brain-state inference. A tree-structured neural network (NeuralTree) classification processor extracts a rich set of neural biomarkers in a patient- and disease-specific manner. Trained with an energy-aware learning algorithm, the NeuralTree classifier detects the symptoms of underlying disorders (e.g., epilepsy and movement disorders) at an optimal energy-accuracy trade-off. A 16-channel high-voltage (HV) compliant neurostimulator closes the therapeutic loop by delivering charge-balanced biphasic current pulses to the brain. The proposed SoC was fabricated in 65nm CMOS and achieved a 0.227μJ/class energy efficiency in a compact area of 0.014mm²/channel. The SoC was extensively verified on human electroencephalography (EEG) and intracranial EEG (iEEG) epilepsy datasets, obtaining 95.6%/94% sensitivity and 96.8%/96.9% specificity, respectively. In-vivo neural recordings using soft μECoG arrays and multi-domain biomarker extraction were further performed on a rat model of epilepsy. In addition, for the first time in literature, on-chip classification of rest-state tremor in Parkinson's disease (PD) from human local field potentials (LFPs) was demonstrated.

Keywords: Machine learning; Parkinson’s disease; closed-loop neuromodulation; decision tree; energy-efficient classification; epilepsy; neural network; seizure; tremor.

Fig. 1.

Versatile closed-loop neural interface platform with high-density sensing and stimulation capabilities.

Fig. 2.

Proposed 256-channel scalable, versatile closed-loop SoC architecture.

Fig. 3.

The relative importance of 128 iEEG channels recorded from an epileptic patient and evaluated with 5-fold cross-validation.

Fig. 4.

The AFE configurations for (a) classifier training with high-density sensing, and (b) channel-selective inference, where any subset of 64 input channels can be selectively processed on a window-by-window basis.

Fig. 5.

Illustration of EDO fluctuations at the input of the proposed TDM AFE in channel-selective inference mode. Among 256 input channels, up to 64 channels with unique EDOs are multiplexed to the AFE in each feature extraction window. Therefore, the AFE must cancel the EDOs that change abruptly between successive channels and feature extraction windows.

Fig. 6.

Modular architecture of the proposed 256-channel CS-TDM AFE with a two-step fast-settling mixed-signal DSL. In training mode, the 4×16 switch matrix in each AFE module sequentially selects 64 input channels (row-major order) for signal conditioning. In each feature extraction window during inference, the four MUX-CHOPs select up to 64 channels out of 256 and route them to the main AFE module via the shared input path drawn in red.

Fig. 7.

Timing diagram of the two-step (coarse/fine) DSL operation in channel-selective inference mode. (a) The coarse EDO cancellation using 9-bit binary search is performed in the first sampling period in each feature extraction window. (b) The ΔΣ fine loop for residual EDO cancellation operates for the rest of the feature extraction window.

Fig. 8.

Circuit implementations of the forward-path amplifiers: (a) core amplifier in the LNA stage and its common-mode feedback (CMFB) circuit, and (b) G_m-C integrator and the timing diagram of operation.

Fig. 9.

Configurable TDM FIR filter and multi-symptom TDM FEE.

Fig. 10.

Hardware implementations of the TDM FEE: (a) temporal and spectral feature extractor, and (b) phase feature extractor.

Fig. 11.

Boxplot of the Pearson correlation coefficients between the ideal and approximated features.

Fig. 12.

NeuralTree classifier: (a) probabilistic NeuralTree trained with energy-aware regularization and network pruning, and (b) the NeuralTree hardware implementation and system operation under the proposed singlepath channel-selective inference scheme. The NeuralTree is trained on neural activity from all 256 channels. Following the regularization and network pruning, each internal node contains an optimal set of up to 64 features, which can be associated with any input channels.

Fig. 13.

Architecture of the HV compliant neurostimulator: (a) 12-stage 4-phase charge pump with high-frequency clocking, and (b) HV compliant H-bridge output driver with charge balancing.

Fig. 14.

(a) Chip micrograph, and (b) SoC power breakdown.

Fig. 15.

Measured AFE performance: (a) programmable gain, (b) programmable high-pass pole, (c) output power spectral density with a single-tone input, (d) input-referred noise spectral density, and (e) two-step fast-settling DSL operation in the presence of abrupt offset changes over three successive 1s windows.

Fig. 16.

Biphasic outputs of the neurostimulator: (a) programmable current amplitude, (b) pulse width, (c) frequency, and (d) in-vitro measured output.

Fig. 17.

The SoC validation on a rat model of epilepsy and human datasets: (a) the experimental setup for in-vivo testing, (b) a 15-channel soft μECoG array with a flexible cable, (c) ECoG recordings and neural biomarker extraction in a normal state, (d) ECoG recordings and neural biomarker extraction in a seizure state, (e) epileptic seizure detection from iEEG, and (f) Parkinsonian tremor detection from LFPs.