L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

Abstract

Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

Fig 1. Average write rate per frame in sets with A live frames as a function of capacity (90%, 75%, and 50%).

Fig 2. Block flow diagram of non-inclusive model.

Fig 3. Block classification regarding its compression ratio for the selected SPEC CPU 2006 and 2017 applications.

Fig 4. Layout of a frame entry in the SRAM tag and NVM data arrays.

Fig 5. Flow of writing a block in L2C2 and components involved.

Fig 6. Flow of reading a block in L2C2 and components involved.

Fig 7. Example of ECB rearranging to write a 9-byte frame.

Fig 8. Per-byte Remaining Writes (A) and Write Rate (B) maps.

Fig 9. Forecasting procedure diagram.

Basic procedure in black, approximations in blue.

Fig 10. Forecasted T_50C (in years) as a function of the number of epochs for frame disabling (A) and L2C2 (B) caches.

Three coefficients of variation are employed: cv = 0.2, 0.25, and 0.3.

Fig 11. Effective capacity evolution over time until 50% of capacity is lost for three different cv.

cv = 0.2 (A), cv = 0.25 (B), cv = 0.3 (C).

Fig 12. Normalized IPC evolution over time until 50% of capacity is lost for three different cv.

cv = 0.2 (A), cv = 0.25 (B), cv = 0.3 (C).

Fig 13. IPC evolution until losing 50% of capacity of an L2C2 without intra-frame wear-leveling mechanism, L2C2-NWL, for cv = 0.2.

Fig 14. IPC evolution until losing 50% of capacity of an L2C2 with LRU-Best-Fit replacement policy, L2C2-BF, for cv = 0.2.

Fig 15. IPC evolution until losing 50% of capacity of FD and L2C2 for cv = 0.2.

Doubling cache size (A), doubling the number of cores while keeping the same 4MB/core (B), and only considering the most memory-intensive programs (C).