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. 2023 Jan 17;14(2):232.
doi: 10.3390/mi14020232.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

G Lakshmi Priya  1   2 , Namita Rawat  2 , Abhishek Sanagavarapu  2 , M Venkatesh  3 , A Andrew Roobert  4
Affiliations

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

G Lakshmi Priya et al. Micromachines (Basel). .

Abstract

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

Keywords: MIM Memristor; Monte-Carlo simulation; low power SRAM; sense amplifier; silicon substrate FinFET.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Three-dimensional view of Silicon substrate based FinFET.
Figure 2
Figure 2
Drain current characteristics of Silicon substrate based FinFET with applied (a) Gate Voltage and (b) Drain Voltage for various channel lengths of L = 32 nm, 45 nm and 90 nm.
Figure 3
Figure 3
Basic model for Memristor [13].
Figure 4
Figure 4
(a) Cross-sectional view of Ti/SiO2/Si(n++)/TiN Memristor. (b) Schematic of Metal-Insulator-Metal (MIM) structure.
Figure 5
Figure 5
Implementation of 6T–CMOS Static RAM (SRAM) design [8].
Figure 6
Figure 6
Implementation of 6T-SRAM design using (a) FinFET [12]. (b) Hybrid MOS–Memristor [22].
Figure 7
Figure 7
Silicon Substrate FinFET–Ti/TiN Memristor based hybrid 6T-SRAM design.
Figure 8
Figure 8
Conventional CMOS 6T-SRAM, (a) DC Analysis, (b) Transient Analysis and (c) Monte Carlo Simulation.
Figure 9
Figure 9
(a) Ti/TiN based Memristor schematic and its (b) I-V Characteristics, (c) Schematic of Memristor–MOS Transistor based Inverter and its (d) Transient Analysis.
Figure 10
Figure 10
Hybrid MOS–Memristor 6T-SRAM design (a) Schematic, (b) DC Analysis, (c) Transient Analysis, and (d) Monte Carlo Simulation.
Figure 11
Figure 11
Silicon Substrate FinFET based 6T-SRAM design (a) Schematic and (b) Transient Analysis.
Figure 12
Figure 12
Proposed hybrid FinFET and Ti/SiO2/Si(n++)/TiN Memristor 6T-SRAM (a) Schematic, (b) DC Analysis, (c) Transient Analysis, and (d) Monte Carlo Simulation.
Figure 13
Figure 13
Read delay comparison of hybrid FinFET and Ti/SiO2/Si(n++)/TiN Memristor 6T-SRAM and traditional SRAM designs for various supply voltages.
Figure 14
Figure 14
Write delay comparison of hybrid FinFET and Ti/SiO2/Si(n++)/TiN Memristor 6T-SRAM and traditional SRAM designs for various supply voltages.
Figure 15
Figure 15
Proposed hybrid FinFET and Ti/SiO2/Si(n++)/TiN Memristor 6T-SRAM. (a) Hold and Read Static Noise Margin (SNM). (b) Write SNM.
Figure 16
Figure 16
Power and Delay comparison of various 6T-SRAM designs with the proposed hybrid Si substrate FinFET–Ti/TiN Memristor.
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References

    1. Ishibashi K., Osada K. Low Power and Reliable SRAM Memory Cell and Array Design. Springer; New Delhi, India: 2011. (Springer Series in Advanced Microelectronics).
    1. Dhanumjaya K., Prasad D.M.G., Padmaraju K., Reddy D.M.R. Design of Low Power SRAM in 45 Nm CMOS Technology. Int. J. Eng. Res. Appl. 2011;1:2040–2045.
    1. Kumar T.S., Tripathi S.L. Leakage Reduction in 18 nm FinFET Based 7T SRAM Cell Using Self Controllable Voltage Level Technique. Wirel. Pers. Commun. 2021;116:1837–1847. doi: 10.1007/s11277-020-07765-6. - DOI
    1. Mann R.W., Zhao M., Kwon O.S., Cao X., Parihar S., Ul Karim M.A., Higman J., Versaggi J., Carter R. Bias-Dependent Variation in FinFET SRAM. IEEE Trans. Very Large Scale Integr. Syst. 2020;28:1341–1344. doi: 10.1109/TVLSI.2020.2974202. - DOI
    1. Zhu J., Bai N., Wu J. Review of Sense Amplifiers for Static Random Access Memory. IETE Tech. Rev. Inst. Electron. Telecommun. Eng. India. 2013;30:72–81. doi: 10.4103/0256-4602.107343. - DOI