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. 2023 Feb 7;23(4):1862.
doi: 10.3390/s23041862.

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation

Louis Colbach  1 , Taekwang Jang  1 , Youngwoo Ji  2
Affiliations

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation

Louis Colbach et al. Sensors (Basel). .

Abstract

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm2.

Keywords: DIBL effect; line sensitivity; subthreshold voltage reference; temperature coefficient; ultra-low-power.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Simulated drain current of different-length PMOS transistors in 180 nm as a function of the drain-source voltage VDS with W/L=10 and |VGS|=100 mV for all cases [7].
Figure 2
Figure 2
Schematic of the proposed voltage reference circuit.
Figure 3
Figure 3
Simulated current biasing of M2.
Figure 4
Figure 4
Linearity of the intermediate voltages VX and VY.
Figure 5
Figure 5
Line sensitivity depending on the width of M4.
Figure 6
Figure 6
Schematic of the proposed circuit, including trimming for minimum line sensitivity.
Figure 7
Figure 7
Simulated variation of VREF versus VDD in the suggested operating range of 0.6 V<VDD<1.8 V.
Figure 8
Figure 8
Simulated output voltage of the proposed voltage reference in comparison with the conventional 2-T reference.
Figure 9
Figure 9
Normalized and magnified output voltages of the proposed design and the conventional 2-T reference.
Figure 10
Figure 10
Monte Carlo simulation results for the line sensitivity of the circuit presented in Figure 2 (400 runs).
Figure 11
Figure 11
Monte Carlo simulation results for the line sensitivity of the circuit presented in Figure 6 using the optimal trimming code for each run (400 runs).
Figure 12
Figure 12
Simulated temperature variation of VREF.
Figure 13
Figure 13
Simulated power consumption.
Figure 14
Figure 14
Simulated PSRR at 25 °C and VDD=0.6 V.
See this image and copyright information in PMC

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