A review of memristor: material and structure design, device performance, applications and prospects

Abstract

With the booming growth of artificial intelligence (AI), the traditional von Neumann computing architecture based on complementary metal oxide semiconductor devices are facing memory wall and power wall. Memristor based in-memory computing can potentially overcome the current bottleneck of computer and achieve hardware breakthrough. In this review, the recent progress of memory devices in material and structure design, device performance and applications are summarized. Various resistive switching materials, including electrodes, binary oxides, perovskites, organics, and two-dimensional materials, are presented and their role in the memristor are discussed. Subsequently, the construction of shaped electrodes, the design of functional layer and other factors influencing the device performance are analyzed. We focus on the modulation of the resistances and the effective methods to enhance the performance. Furthermore, synaptic plasticity, optical-electrical properties, the fashionable applications in logic operation and analog calculation are introduced. Finally, some critical issues such as the resistive switching mechanism, multi-sensory fusion, system-level optimization are discussed.

Keywords: Artificial intelligence; device performance; in-memory computing; material and structure design; memristor.

Graphical abstract

Scheme 1.

Memristor: RS materials, structure design, performances, and applications. Reproduced with permission from [15,16] copyright 2021, Wiley, [17] copyright 2021, American Chemical Society, [18] copyright 2021, Springer Nature, [19] copyright 2021, American Chemical Society, [20] copyright 2018, Royal Society of Chemistry, [21] copyright 2022, Elsevier, [22] copyright 2020, Springer Nature, [23] copyright 2020, American Chemical Society, [24] copyright 2019, Wiley, [25] copyright 2022, American Chemical Society, [26] copyright 2022, Wiley.

Figure 1.

(a) I–V characteristic for ITO/SnO₂/TiN and ITO/Bi: SnO₂/TiN memristors. (b) The on/off state resistance ratio for ITO/SnO₂/TiN and ITO/Bi: SnO₂/TiN memristors. Reproduced with permission from [69], copyright 2020, Wiley. (c) Typical I–V curves of the ITO/TiO₂/HfO₂/Pt resistive RRAM. The inset is a schematic diagram of the device. (d) LRS/HRS resistances for the ITO/TiO₂/HfO₂/Pt RRAM under tensile strain with different bending radius. Inset: Photograph of the ITO/TiO₂/HfO₂/Pt RRAM on polyvinyl naphthalate substrate. Reproduced with permission from [49], copyright 2019, Wiley. (e) 100 sequential I–uV curves for the Pt/HfO₂/BFO/HfO₂/TiN and the Pt/HfO₂/TiN devices. The inset is schematic diagram of RS mechanism of the Pt/HfO₂/BFO/HfO₂/TiN during the set process. (f) High-resolution TEM image of a Hf nanofilament, inserts: images of FFT patterns for hexagonal crystal Hf in the functional layer of Pt/HfO₂/BFO/HfO₂/TiN device. Reproduced with permission from [16], copyright 2021, Wiley.

Figure 2.

(a) (i) Schematic showing the MAPbI₃ quantum wires (QWs)/nanowires (NWs) in a porous alumina membrane stacked between crisscrossed Ag/ITO and Au finger electrodes, supported by a polyethylene terephthalate substrate. (ii) An enlarged view of an individual QW comprising the Ag filament sandwiched between ITO/Ag and Au contacts. (iii) Crystal structure of MAPbI₃. (b) Schematic diagram of MAPbI₃ QWs memory device. Insert: Highly magnified cross-sectional view of 153 nm² device after Ag evaporation showing the distinct SiO₂ layer between the Ag electrode and MAPbI₃QWs. Reproduced with permission from [17], copyright 2021, American Chemical Society. (c) Schematic diagram of the Cs₂AgBiBr₆-based device. I–V characteristics of Cs₂AgBiBr₆-based device in different harsh environments: (d) Burnt by luminous cone of alcohol lamp for 10 s. (e) Heated from 303 to 453 K. (f) Exposed under ⁶⁰Co γ-ray irradiation with a total dose of 5 × 10⁵ rad (SI). Reproduced with permission from [94], copyright 2019, Wiley.

Figure 3.

(a) Mechanical and electrical performances of the developed organic memristor. Reproduced with permission from [104], copyright 2021, Wiley. (b) Schematic illustrations of the array consisting of pV₃D₃/Al₂O₃ memristors and their multiply-accumulate operations. Reproduced with permission from [105], copyright 2022, Wiley. (c) Textile chip made from DNA-bridged memristor cross-bar arrays. Each contact point represents a memristor. (d) Photograph and the operation mechanism of a proof-of-concept all-fabric data-processing system. Scale bars in (e) is 0.5 cm. Reproduced with permission from [106], copyright 2020, Wiley.

Figure 4.

(a) Schematic of an ITO/PVA-GO/ITO memristor, where PVA stands for poly(vinyl alcohol) and GO for graphene oxide. Reproduced with permission from [112], copyright 2020, Wiley. (b) Schematic of an Ag/InSe/Ag memristor. Inset is the optical image of the device with a channel length of 8 μm. Reproduced with permission from [113], copyright 2021, AIP Publishing LLC. (c) Sandwich-like structure of the TiS₃-based memristor. Reproduced with permission from [17], copyright 2021, American Chemical Society. (d) Schematic diagram of the WS₂/MoS₂ heterojunction memristor. Reproduced with permission from [111], copyright 2021, Royal Society of Chemistry. (e) The typical structure of Al/Ti₃C₂: Ag/Pt device. Reproduced with permission from [114], copyright 2021, Elsevier. (f) Schematics of the multilayer Gr/MoS₂(MGM) cellulose paper memory. Reproduced with permission from [115], copyright 2019, American Chemical Society.

Figure 5.

(a) Schematic drawing of a NiO RRAM cell device composed of an Nb nanopin bottom electrode, a NiO thin film, and an Nb top electrode. The thickness (d) of the NiO film is about 80 nm. Inset: A scanning electron microscopy image of the Nb nanopin array. Reproduced with permission from [20], copyright 2018, Royal Society of Chemistry. (b) Schematics of the W/AlO_x (RF)/Al₂O₃ (ALD)/Pt memristor with 250 nm via-hole structure. Reproduced with permission from [135], copyright 2020, IEEE. (c) The structure of the W/MgO/SiO₂/Mo memristor. Reproduced with permission from [15], copyright 2021, Wiley. (d) A schematic of a 1D1R memory device. (e) IV characteristics of a 1D1R memory device. Reproduced with permission from [136], copyright 2010, Wiley. (f) 3D schematic of 1S1R integration crossbar arrays. The enlarged view is a vertical stacking cell of a selector and a memristor with top, middle, and bottom electrodes. (g) Typical I–V curves of the integrated 1S1R cell, where the forming process and normal operation cycles are included. Reproduced with permission from [137], copyright 2019, Wiley.

Figure 6.

(a) Scanning electron microscopy top-view image of the fabricated circuit with a zoom on a stacked Pt/Al₂O₃/TiO_2–x/TiN/Pt memristors to highlight the clean electrode edges. (b) Equivalent circuit for two Pt/Al₂O₃/TiO_2–x/TiN/Pt memristors in the stacked configuration, in particular, highlighting that the middle electrode (gray) is shared between bottom (red) and top (blue) devices. The cross-section photograph showing the material layers and their corresponding thicknesses. Reproduced with permission from [155], copyright 2017, IEEE. (c) (i) 3D monolithic integrated memristor circuits. Schematic of the 3D circuits composed of high-density staircase output electrodes (blue) and pillar input electrodes (red). (ii) Sideview of 3D row banks. Each row bank in the 3D array operates independently. (iii) Sideview from column side showing unique staircase electrodes. Reproduced with permission from [22], copyright 2020, Springer Nature. (d) An optical image of a wafer with transistor arrays. (e) Close-up of chip image showing arrays of various sizes. (f) Microscope image showing the 1T1 R structureof the cell. Scale bar, 10 µm. (g) Cross-sectional scanning electron microscopic image of an individual 1T1R cell, which is cut in a focused ion beam microscope from the dashed line in (g). Scale bar, 2 µm. (h) Cross-sectional transmission electron microscopic image of the integrated Ta/HfO₂/Pt memristor. Scale bar, 2 nm. Reproduced with permission from [141], copyright 2018, Springer Nature.

Figure 7.

(a) Repeatable 100 cycles of Ag/TiN/HfO_x/HfO_y/HfO_x/TiN/Ag device under an I_CC of 3 mA, indicating an extremely high ON/OFF ratio of over 10¹⁰. Reproduced with permission from [162], copyright 2022, Wiley. (b) Endurances of HfO₂-based memristors before and after inserting the BFO layer. Reproduced with permission from [61], copyright 2020, Wiley. (c) The power consumption variation of Ti₃C₂ and Ti₃C₂: Ag devices. Reproduced with permission from [114], copyright 2021, Elsevier. (d) Cumulative probability distribution of 1,024 cells with respect to 32 independent conductance states. Reproduced with permission from [163], copyright 2020, Springer Nature. (e) Switching characteristics of TiN/HfO₂/ITO device for 10 switching cycles. The inset shows a schematic diagram of the device. Reproduced with permission from [164], copyright 2014, IOP. (f) The DC I-V characteristic of the flexible Pt/Hf_17.66Ti_13.79O_68.55/ITO selector device in 100 voltage sweep cycles. Reproduced with permission from [165], copyright 2019, Royal Society of Chemistry.

Figure 8.

(a) EPSC triggered by positive gate voltage pulses with different widths. Insert: schematic of organic field-effect transistor [191]. (b) The learning experience behaviors of Cu/SiC/W memristor for the learning/forgetting process [192]. (c) The repeated LTP and LTD characteristics of the device demonstrating good stability with minimal cycle-to cycle variations. (d) PPF index obtained by applying paired pulses [193]. (e) Asymmetric Hebbian STDP rule obtained in HfO₂/BFO/HfO₂ memristor [16].

Figure 9.

(a) Schematic showing light modulation of the BP@PS memristor. (b) I-V curves of the BP@PS memristor modulated by different wavelengths. Reproduced with permission from [23], copyright 2020, American Chemical Society. (c) Schematic of the realization of an AOC memristor. MC and NIR denote the memconductance and near-infrared, respectively. (d) Reversible regulation of the memconductance by means of 100 blue light pulses (D = 1 s, I = 1 s, and P = 20 µw cm⁻²) and 100 NIR light pulses (D = 1 s, I = 1 s, and P = 24 µw cm⁻²). Reproduced with permission from [191], copyright 2021, Wiley. (e) Integration of the h-BN/WSe₂ optic-neural synaptic device. A Schematic of the human optic nerve system, the h-BN/WSe₂ synaptic device integrated with h-BN/WSe₂ photodetector, and the simplified electrical circuit for the ONS device. Here, the light sources were dot lasers with wavelengths of 655 nm (red), 532 nm (green), and 405 nm (blue) with a fixed power density (P) of 6 mW cm⁻² for all wavelengths. (f) Left: Developed ONN for recognition of 28 × 28 RGB-colored images. Right: Recognition rate as a function of number of training epochs for ONN and conventional NN. Reproduced with permission from [192], copyright 2018, copyright 2021, Springer Nature.

Figure 10.

(a) Au/h-BN/Au memristors array and IMP logic implementation. The color map plots of the resistance distribution of the 8 × 8 memory array fabricated via (a) Direct metal evaporation and (b) Metal transfer technique. (c) Schematic of the IMP logic circuit. V_SET and V_COND are simultaneously applied to memristors Q and P, respectively. RG is chosen to be 500 Ω. (d) Experimental results of IMP operations for four input conditions. p and q are the resistance states of device P and Q, respectively. “1” refers to low-resistance state and “0” refers to high-resistance state. p′ and q′ are the states of device P and Q, respectively after the logic operations. Variable p remains unchanged because V_COND is lower than V_SET, so p and p′ should have the same value. The readout voltage is 0.1 V. (e) True table of the logic operation. Reproduced with permission from [202], copyright 2022, Wiley. (f) Photograph of the PUF system. ZC706 FPGA evaluation board from Xilinx is used. The chip contains an 8-kb memristor array and supports parallel operation for up to eight memristor devices. (g) The change in CC between binary PUF data (top left inset) and analog resistance values measured in secure mode (top right inset). (h) The change of prediction accuracy with incremental training epoch for traditional NVM PUF, whose data are steadily stored by distinct high and low conductance states, and the developed concealable PUF. Reproduced with permission from [203], copyright 2022, American Association for the Advancement of Science.

Figure 11.

(a) (i) Artificial somatosensory system consisting of an MFSN array and an SNN classifier to emulate tactile perception. (ii) the MFSN unit is composed of a pressure sensor and a NbO_x-based memristor. The output frequency of the MFSN unit is affected by the pressure intensity and temperature, while the output amplitude of spikes depends only on the temperature. (b) Schematic of an SNN comprising 400 input neurons, 50 hidden neurons, and 8 output neurons for the simulation. (c) Evolution of the training accuracy with training epoch at three different modes (pressure, temperature, and multimodal mode). (d) Confusion matrix of simulation classification output versus the expected outputs. The result shows the good classification ability of the MFSN-based system. Reproduced with permission from [212], copyright 2022, Wiley. (e) Three different types of 3 × 3 kernel operation (edge detection, sharpen and soften) are performed. (f) Corrupted letter images are generated by adding Gaussian noise (δ = 0.5) to images from the eye layer. (g) Letter images are denoised by inserting a denoising layer that includes memristor crossbar arrays, as described in the block diagram. Reproduced with permission from [221], copyright 2022, Springer Nature.

Figure 12.

Design methodology and main features of the NeuRRAM chip. (a) Cross-layer co-optimizations across the full stack of the design enable NeuRRAM to simultaneously deliver high versatility, computational efficiency and software-comparable inference accuracy. (b) Micrograph of the NeuRRAM chip. (c) Reconfigurability in various aspects of the design enables NeuRRAM to implement diverse AI models for a wide variety of applications. (d) Comparison of EDP, a commonly used energy-efficiency and performance metric among recent RRAM-based CIM hardware. (e) Fully hardware-measured inference accuracy on NeuRRAM is comparable to software models quantized to 4-bit weights across various AI benchmarks. Reproduced with permission from [226], copyright 2022, Springer Nature.