Co-packaged optics (CPO): status, challenges, and solutions

Abstract

Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology.

Keywords: Advanced packaging; Co-packaged optics; Co-simulation; External laser; High-performance computing; Optical power delivery; Receiver; Silicon photonics; Standardization; Transmitter.

Fig. 1

Schematic of CUMEC silicon photonics PDK

Fig. 2

Hybrid packaging of PM fibers for light input and non-PM fibers for light output

Fig. 3

a Heterostructure integration [30] and b heterogenous integration [33] of on-chip light source

Fig. 4

a Hybrid-assembled optical module using silicon photonic interposer with TSV structures [10]. b TSV fabrication process on silicon photonics interposer [35]

Fig. 5

Configuration of co-packaged optics for 102.4 T

Fig. 6

Performance of high-power laser

Fig. 7

Challenges of optical power delivery illustrated by a simple optical link

Fig. 8

a Pluggable optical module [13]. b Architecture of CPO [13]

Fig. 9

XSR top-level structure block diagram and XSR applications and requirements

Fig. 10

LR architecture and performance requirements

Fig. 11

Clock path

Fig. 12

a Terminal of the transceiver. b TX with T-coil Peaking [97]. c RX with T_coil and inductive peaking [99]. d RX with LC-π network [100]

Fig. 13

a Equalizers in ADC-DSP based SerDes. b DF-NL-MLSE [104]

Fig. 14

The diagram of MRR-based transceiver consisting of drivers, MRMs, receivers, MRR DEMUX, and thermal tuners

Fig. 15

NRZ pluggable vs. PAM-4 CPO transceiver, red: SiGe, blue: CMOS, purple: silicon photonics

Fig. 16

Bandwidth growth of Switch and ASIC in the last decade [4]

Fig. 17

Full assembly of co-packaged switch, showing sixteen transceiver modules

Fig. 18

CPO solutions. a IBM and II-VI. b Ranovus. c Intel. d Ayar-labs. e Hengtong Rockley

Fig. 19

Optoelectronic 3D integration cross section a 2.5D solution. b 3D solution

Fig. 20

Schematic diagram of XSR-AUI CPO [85]

Fig. 21

Development of physical layer

Fig. 22

Architecture of the extended physical layer

Fig. 23

When CPU needs more I/O bandwidth but is limited by package, Optic I/O can help to solve the problem

Fig. 24

Technology maturity levels on optical connectivity [80]

Fig. 25

Scene of the 1st Conference of Chinese Interconnect Technology and Application

Fig. 26

CCITA CPO and chiplet standard outline