A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

Abstract

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

Fig. 1. Design of heterojunction non-volatile memory transistor (H-MTR) and binary/ternary reconfigurable logic inverter (R-inverter).

a A schematic illustration of the H-MTR. b A cross-sectional high-resolution transmission electron microscope (HRTEM) image of the H-MTR. False color modification was applied to distinguish each layer. c A schematic diagram illustrating the charge injection at drain electrode in the H-MTR with the (+) programmed state (left) and d (−) programmed state (right). Red sphere represents electron carrier. e A conceptual schematic illustrating the operating principle of the R-inverter.

Fig. 2. Investigation of the device characteristics according to each programmed state.

a The transfer characteristics, b peak voltage (V_Peak) and valley voltage (V_valley), and c peak current (I_Peak) and valley current (I_Valley) of the H-MTR with respect to (−) programming voltage (−V_prg). d The transfer characteristics, e V_Peak and V_valley, and f I_Peak and V_Valley of the H-MTR with respect to (+) programming voltage (+V_prg). Curves of different colors correspond to different V_prg.

Fig. 3. R-inverter.

a A schematic illustration of the R-inverter. b An optical microscopy image of the inverter. (scale bar: 500 µm). c Voltage transfer characteristics (VTC), and d DC gain profiles of the R-inverter with respect to −V_prg. e Butterfly inverter curve of the inverter with ternary operation (V_prg = −15 V). f VTC, and g DC gain profiles of the R-inverter with respect to +V_prg. h Butterfly inverter curve of the inverter with binary operation (V_prg = +18 V). i Output voltage (V_OUT) of intermediate logic state (input voltage (V_IN) = 3.5 V), j 1st and 2nd transition voltages (V_trans), and k 1st and 2nd DC gain values of R-inverter with respect to V_prg.

Fig. 4. Stability of the R-inverter.

a VTCs of repetitive transition between ternary and binary logic operations up to 25 cycles. b Extracted V_OUT values at V_IN = 0 V, 3 V, and 6 V from each cycle of ternary logic operation. c Extracted V_tran from each cycle of binary logic operation. d The change in VTCs with ternary operation and e binary operation vs. time. f The change in static noise margin (SNM) of ternary operation and binary operation vs. time.

Fig. 5. Binary/ternary logic conversion-in-memory.

a A schematic symbol of logic conversion-in-memory. b Overlapped transfer characteristics of the H-MTR for V_prg = −15 V (dotted line) and V_prg = +18 V (solid line) and n-type transistor. Here, 75 nm-thick DNTT was used. c VTCs of the corresponding inverter. V_prg = −15 V (dotted line) and V_prg = +18 V (solid line). d A schematic symbol of two-stage R-inverter and its truth table. e Pulsed measurement of two-stage R-inverter with three different configurations (ternary-ternary, binary-ternary, and ternary-binary/binary-binary).