A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse

Abstract

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm² and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart.

Keywords: CMOS; Internet of Things; artificial intelligence; artificial neural networks; leaky integrate and fire; neuromorphic; spiking neural network.

Figure 1

An LIF-based neuronal model of CMOS neuron cell.

Figure 2

The architecture of the proposed SNN chip consists of four fully connected layers.

Figure 3

Proposed neuron circuit based on LIF.

Figure 4

The schematic of the CMCI-based synapse circuit.

Figure 5

Simulation results for single neuron cell where (a) is the enable signal of 15 input spike signals, (b) V_mem along with output spike for weight values +1, 0 and −1, (c) V_mem along with output spikes for weight values +15 and −15.

Figure 6

The micrograph of SNN chip with complete layout.

Figure 7

Measurement setup of (a) analog and (b) digital SNNs.

Figure 8

Spike signals of SNN chip measured by a logic analyzer: (a) One input spike signal propagation; (b) 15 input spike signals propagation.

Figure 9

Measured classification result for digital SNN.