Process integration and future outlook of 2D transistors

Abstract

The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the recent progress in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices based on stacked 2D TMD nanoribbons and specifically highlight issues that still need to be resolved by the 2D community in five crucial research areas: contacts, channel growth, gate oxide, variability, and doping. While 2D TMD transistors have great potential, more research is needed to understand the physical interactions of 2D materials at the atomic scale.

Fig. 1. Comparisons of subthreshold swing (SS) versus channel length for various transistor geometries illustrating the advantage of 2D nanosheets.

The simulation of SS for semiconductor geometries (Planar, FinFET, nanoribbon, and 2D nanosheet) versus Leff (gate length) shows competitive electrostatics of 2D transition metal dichalcogenides compared to Si at sub-10 nm physical gate lengths. The 2D nanosheet SS is calculated using atomistic density functional theory, whereas the other geometries are from electrostatic solutions.

Fig. 2. Illustrations of stacked nanoribbon transistors with the same physical height.

a Cross-section image of a stacked gate-all-around (GAA) Si compared to stacked GAA 2D TMD nanoribbon (NR) transistors with the same physical height. Assuming the same volume for gate oxide and gate metal deposition, four stacked Si NR would have the same height as six stacked 2D TMD NR. Therefore, 2D TMD drive currents need only be 2/3 of Si drive currents to be competitive. Panel b represents the same drawing but at the scale of individual atoms for the 2D TMD films. Metal contacts are represented in grey, the spacer dielectric is represented in yellow and the gate oxide is represented in pink. The gate metal is not represented. © IEEE (2023). Figure 2a reprinted with minor modifications, with permission, from K. P. O’Brien et al., “Advancing 2D monolayer CMOS through contact, channel and interface engineering,” 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 7.1.1–7.1.4, 10.1109/IEDM19574.2021.9720651.

Fig. 3. Simplified 2D TMD stacked NR integration scheme with the 2D TMD deposited or transferred onto a sacrificial oxide.

We restrict the image to only include two stacked NRs for illustrative purposes. The red colour represents the TMD, whereas the light blue colour represents a sacrificial film (which can be an oxide or another material). a Etching of the stacked 2D TMD NRs. b Lateral etching opening up the source and drain contact regions to form the inner spacer. 2D TMDs under the spacer must be doped for the transistor to operate properly. c Formation of metal contacts (blue and yellow layers) by a damascene process. Further, it is possible to recess the spacer layer (black) to expose a wider region of the TMD film and enable non-edge contacts. d Gate formation by etching access via to fill the gate oxide (light grey) and metal (dark grey) with an atomic layer deposition (ALD) process. The reader is cautioned that gate oxide depositions present unique challenges due to the nature of 2D TMD van der Waals materials. Typical ALD processes depend on dangling bonds for material nucleation but defect-free 2D TMDs do not have dangling bonds.

Fig. 4. Transmission electron microscopy (TEM) cross-section images of 2D TMD nanoribbons.

a 2D TMD NR with GAA oxide and metal, with 10nm size bar. b–d Four stacked 2D WSe2 NRs with Se and W TEM HAADF signals.