Nano-scale charge trapping memory based on two-dimensional conjugated microporous polymer

Abstract

There is a growing interest in new semiconductor nanostructures for future high-density high-performance flexible electronic devices. Two-dimensional conjugated microporous polymers (2D-CMPs) are promising candidates because of their inherent optoelectronic properties. Here, we are reporting a novel donor-acceptor type 2D-CMP based on Pyrene and Isoindigo (PI) for a potential nano-scale charge-trapping memory application. We exfoliated the PI polymer into ~ 2.5 nm thick nanoparticles (NPs) and fabricated a Metal-Insulator-Semiconductor (MIS) device with PI-NPs embedded in the insulator. Conductive AFM (cAFM) is used to examine the confinement mechanism as well as the local charge injection process, where ultrathin high-κ alumina supplied the energy barrier for confining the charge carrier transport. We have achieved a reproducible on-and-off state and a wide memory window (ΔV) of 1.5 V at a relatively small reading current. The device displays a low operation voltage (V < 1 V), with good retention (10⁴ s), and endurance (10³ cycles). Furthermore, a theoretical analysis is developed to affirm the measured charge carriers' transport and entrapment mechanisms through and within the fabricated MIS structures. The PI-NPs act as a nanoscale floating gate in the MIS-based memory with deep trapping sites for the charged carriers. Moreover, our results demonstrate that the synthesized 2D-CMP can be promising for future low-power high-density memory applications.

Figure 1

Synthetic approach for the rationally designed Pyrene-Isoindigo 2D-CMP (PI).

Figure 2

A schematic of the fabricated MIS structure with the embedded PI–NPs, showing the process flow.

Figure 3

(a) Topography AFM scans in AC mode of the surface with the spin-coated PI–NPs on top of the Al₂O₃ BO along with the associated. (b) AFM scan of the BO before spin-coating and the RMS roughness. (c) Height and (d) mean radius distribution of PI–NPs.

Figure 4

(a) Cross-sectional transmission electron microscopy (XTEM) image of the Pt-coated structure, showing the fabricated MIS stack with the embedded PI–NPs. (b) EELS compositional mapping of the stack.

Figure 5

(a) The circuit of surface mapping and electrical probing of a single PI–NP using conductive-AFM. Inset shows a cross-section view of the probed MIS stack with and without the PI–NP.

Figure 6

2.5 × 2.5 µm² current maps of the (a) initial, (b) write, (c) read, (d) erase and (e) read scans.

Figure 7

I-V characteristics for two successive sweeps at points A and B of the (a) MIS_A stack, as well as for points C and D of the (b) MIS_B stack.

Figure 8

Six sets of successive write (green), read (red), erase (blue) IV sweeps. Inset highlights a memory window of 1.46 V at 200 pA.

Figure 9

(a) IV sweeps of MIS_A structure throughout the endurance test at V_W/E =  ± 4 V after 1, 110, 170 and 210 cycles. (b) Endurance characteristics for 210 W/E cycles extracted at V_Read = 0.8 V from IV sweeps. (c) Retention characteristics up to 10⁴ s at V_W/E =  ± 4 V and V_Read = 0.8 V.

Figure 10

IV sweeps at different voltage biases. Inset shows the memory window vs bias voltage.

Figure 11

Capacitance at different dielectric constant values of PI.

Figure 12

Variation in charge trap density with (a) applied gate voltage (V_g) and (b) change in threshold voltage (ΔV_th) for different dielectric constants of PI.

Figure 13

(a) Variation in Electric field across the tunneling oxide with gate voltage for the different dielectric constant of PI. (b) Variation in natural log of (ΔV_th/E) with (1/E) across the tunneling oxide for ε_PI = 3.0.

Figure 14

The energy band diagram for (a) flat band state, (b) charge injection during write operation, (c) charge screening, and (d) charge ejection during erase operation within the embedded PI–NP when probed using a conductive AFM Tip. The varying thickness of the red arrows symbolizes the magnitude of tunneling current.