Roadmapping the next generation of silicon photonics

Abstract

Silicon photonics has developed into a mainstream technology driven by advances in optical communications. The current generation has led to a proliferation of integrated photonic devices from thousands to millions-mainly in the form of communication transceivers for data centers. Products in many exciting applications, such as sensing and computing, are around the corner. What will it take to increase the proliferation of silicon photonics from millions to billions of units shipped? What will the next generation of silicon photonics look like? What are the common threads in the integration and fabrication bottlenecks that silicon photonic applications face, and which emerging technologies can solve them? This perspective article is an attempt to answer such questions. We chart the generational trends in silicon photonics technology, drawing parallels from the generational definitions of CMOS technology. We identify the crucial challenges that must be solved to make giant strides in CMOS-foundry-compatible devices, circuits, integration, and packaging. We identify challenges critical to the next generation of systems and applications-in communication, signal processing, and sensing. By identifying and summarizing such challenges and opportunities, we aim to stimulate further research on devices, circuits, and systems for the silicon photonics ecosystem.

Fig. 1. Timeline for the number of components on a silicon photonic integrated circuit (PIC) over generations of small-scale, medium-scale, large-scale, and very-large-scale integration (SSI, MSI, LSI, VLSI, respectively).

A component is a unit cell that is combined with other unit cells to build a circuit, such as a waveguide, directional coupler, heater, grating coupler, etc. Heterogeneous silicon photonics lags hybrid by approximately two years. For comparison, data for InP-based integrated photonics is also shown. In general, the higher the number of high-speed modulators, the more challenging the scaling. The figure is adapted from refs. ^,.

Fig. 2. Illustrative renditions of LSI silicon photonic systems capturing current and future technologies.

a WDM Transceiver: A semiconductor mode-locked laser (SMLL) provides multi-wavelength continuous-wave (CW) light to an array of compact, WDM-capable modulators and filters. Reflection control circuits limit back reflections into the laser. High-speed photodetectors (PDs) carry out the O/E conversion. b The electrical current is then amplified by transimpedance amplifiers (TIAs) and limiting amplifiers. Analog-to-digital converters (ADCs) are used to digitize the signal for further digital signal processing (DSP). Monitoring PDs are used for control and stabilization of wavelength, phase shift, and temperature. Digital-to-analog converters (DACs) and drivers are used for E/O modulation of the digital signal. Dynamic random-access memory (DRAM) provides large memory access. Micro-controllers (μC) may be used to offload some of the digital processing as well. c LIDAR: A tunable laser provides frequency chirped light to a network of phase shifters, circulators/duplexers and coherent frontend for homodyne/heterodyne frequency-modulated CW (FMCW) ranging and detection. Beam steering is done using optical phase arrays (OPAs) or focal-plane arrays (FPAs). Delay line interferometers aid in calibrating the received beat frequencies and support chirp linearization by directly controlling the tunable laser or a modulator and various forms of error correction through DSP.

Fig. 3. Techniques to attach a laser to a silicon PIC.

a Conventional laser-isolator (ISO)-fiber-PIC with free-space optics (FSO). b Hybrid 2.5D with FSO. c Hybrid 2.5D with photonic wire bonding (PWB). d Hybrid 3D (flip chip or transfer printing). e Heterogenous (Direct bonding or transfer printing). f Monolithic (Hetero-epitaxy).

Fig. 4. Comparing different techniques to attach a PIC to an electronic IC (EIC).

a Electrical wire bonding (EWB) side-by-side. b 2.5D flip-chipped side-by-side or stacked. c Hybrid 3D TSV (Through-Silicon Via). d Heterogenous 3D with TOV (Through-Oxide Via). e Monolithic electronic photonic IC (EPIC).