Neural flip-flops I: Short-term memory

Abstract

The networks proposed here show how neurons can be connected to form flip-flops, the basic building blocks in sequential logic systems. The novel neural flip-flops (NFFs) are explicit, dynamic, and can generate known phenomena of short-term memory. For each network design, all neurons, connections, and types of synapses are shown explicitly. The neurons' operation depends only on explicitly stated, minimal properties of excitement and inhibition. This operation is dynamic in the sense that the level of neuron activity is the only cellular change, making the NFFs' operation consistent with the speed of most brain functions. Memory tests have shown that certain neurons fire continuously at a high frequency while information is held in short-term memory. These neurons exhibit seven characteristics associated with memory formation, retention, retrieval, termination, and errors. One of the neurons in each of the NFFs produces all of the characteristics. This neuron and a second neighboring neuron together predict eight unknown phenomena. These predictions can be tested by the same methods that led to the discovery of the first seven phenomena. NFFs, together with a decoder from a previous paper, suggest a resolution to the longstanding controversy of whether short-term memory depends on neurons firing persistently or in brief, coordinated bursts. Two novel NFFs are composed of two and four neurons. Their designs follow directly from a standard electronic flip-flop design by moving each negation symbol from one end of the connection to the other. This does not affect the logic of the network, but it changes the logic of each component to a logic function that can be implemented by a single neuron. This transformation is reversible and is apparently new to engineering as well as neuroscience.

Fig 1. Network symbols.

A. A logic circuit illustrated with standard logic symbols. Each of the four components represents a logic function that can be implemented with electronic hardware or with a single neuron. B. The same logic circuit illustrated with symbols commonly used in neuroscience schematic diagrams.

Fig 2. Noise-reducing AND-NOT function.

The graphs show an example of a neuron response to analog inputs that reduces moderate levels of additive noise in binary inputs. A. A sigmoid function f(x) = (1/2)sin(π(x—1/2)) + 1/2. B. Graph of a function that has the noise-reducing properties 1 and 2. The function is F(X, Y) = f(X)—f(Y), bounded by 0. Wireframe: Graph of the response function Z = F(X, Y). Green and red: A triangle in the plane Z = X—Y. Red: Approximate intersection of the plane and the graph of F. Purple: Approximate region in the unit square where F(X, Y) > X—Y (condition 1). Blue: Approximate region in the unit square where F(X, Y) < X—Y or F(X, Y) = 0 (condition 2).

Fig 3. Single transistor AND-NOT gate that reduces noise.

This minimal logic circuit satisfies the noise-reducing conditions 1 and 2. A. A logic circuit consisting of one transistor and three resistors. B. Engineering software simulation. Wireframe: Graph of the transistor response function Z = F(X, Y). Green and red: A triangle in the plane Z = X—Y. Red: Intersection of the plane and the graph of F. Purple: Region in the unit square where F(X, Y) > X—Y (condition 1). Blue: Region in the unit square where F(X, Y) < X—Y or F(X, Y) = 0 (condition 2).

Fig 4. Neural logic gates and flip-flops.

A. A symbol for an AND-NOT logic gate, with output X AND NOT Y. The symbol can also represent a neuron with one excitatory input X and one inhibitory input Y. B. An AND-NOT gate configured as a NOT gate, or inverter. C. A NAND gate (NOT AND). The output is NOT (X AND Y). There is no obvious way to implement this gate with a single neuron. D. A standard design for an electronic active low Set-Reset (SR) flip-flop composed of two NAND gates. E. An active low Set-Reset (SR) flip-flop composed of two AND-NOT gates. This design is derived from the design in D by moving each negation circle from one end of the connection to the other. This inverts the outputs. F. An active high SR flip-flop.

Fig 5. Simulation of an NFF operation with noise in the inputs.

This simulation of the NFF in Fig 4F shows the NFF’s operation is robust in the presence of moderate levels of additive noise in binary inputs. The effect of baseline noise on the memory bit is negligible, and temporary bursts of larger noise have no lasting effect.

Fig 6. Neural memory bank.

Three NFFs (Fig 4F) are enabled by a fourth NFF serving as an on-off switch.