Optimizing quantum gates towards the scale of logical qubits

Abstract

A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental roadblocks are manufacturing high-performance quantum hardware and engineering a control system that can reach its performance limits. The control challenge of scaling quantum gates from small to large processors without degrading performance often maps to non-convex, high-constraint, and time-dynamic control optimization over an exponentially expanding configuration space. Here we report on a control optimization strategy that can scalably overcome the complexity of such problems. We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunable superconducting qubits to execute single- and two-qubit gates while mitigating computational errors. When combined with a comprehensive model of physical errors across our processor, the strategy suppresses physical error rates by ~3.7× compared with the case of no optimization. Furthermore, it is projected to achieve a similar performance advantage on a distance-23 surface code logical qubit with 1057 physical qubits. Our control optimization strategy solves a generic scaling challenge in a way that can be adapted to a variety of quantum operations, algorithms, and computing architectures.

Fig. 1. Frequency optimization.

a Our quantum processor with N = 68 frequency-tunable superconducting transmon qubits represented as a graph. Nodes are qubits (e.g., black dot) and edges are engineered interactions between them (e.g., blue and green bars). b A quantum algorithm (A) comprising single- and two-qubit gates with one qubit (q_j) distinguished. c Corresponding qubit frequency trajectories (F), parameterized by single-qubit idle (f_j for qubit q_j) and two-qubit interaction (f_ij for q_i and q_j) frequencies. Quantum computational errors depend strongly on frequency trajectories since most physical error mechanisms are frequency dependent (red dots are non-exhaustive examples). Namely, pulse distortion errors (1) increase with larger frequency excursions. Relaxation errors (2) increase near relaxation hotspots, for example due to two-level-system defects (TLS, horizontal resonance). Stray coupling errors (3) increase near frequency collisions between coupled computational elements. Dephasing errors (4) increase towards lower frequencies, where qubit flux-sensitivity grows. d We leverage our understanding of physical error mechanisms (M) to estimate the algorithm’s error (E) and then optimize it with respect to qubit frequency trajectories. e We employ the Snake optimizer, which can solve optimization problems at an arbitrary dimension (D), controlled by the scope parameter (S). These graphs show possible idle (nodes) and interaction (edges) frequency optimization variables (blue) at one Snake optimization step for scopes ranging from $S=S_{\max }$ (global limit, ∣F∣D optimization) to S = 1 (local limit, 1D optimization). f Snake optimization threads (progress horizontally) for three scopes (increase downwards). Snake’s high configurability enables it to scalably overcome frequency optimization complexity and be adapted to a variety of quantum operations, algorithms, and architectures.

Fig. 2. Optimization and healing performance.

a CZXEB cycle error benchmarks (e_c, boxes, left axis) and calibration failures (gray bars, right axis in (c)) for the random baseline (red), outlier (orange diamond), and crossover (green) performance standards used to evaluate frequency configurations and our optimization strategy. Each box shows the 2.5, 25, 50, 75, and 97.5th percentiles and mean (see annotations on the baseline). The standards' means are extended across panels for comparison. b Benchmarks for configurations optimized at different scopes (S) ranging from S = 1 (local limit, 1D optimization) to $S=S_{\max }$ (global limit, ∣F∣D optimization). Intermediate dimensional optimization (2 ≤ S ≤ 4) outperforms both local and global optimization, finding configurations near the crossover standard. S = 4 (≤21D optimization) performs best, with the lowest mean error, but S = 2 (≤5D optimization) offers a better balance between performance and runtime, and is set as our default. c Benchmarks for each configuration in (b) after healing, which significantly suppresses performance outliers. Each box in (a), (b), and (c) corresponds to a distinct configuration. d Benchmark heatmaps illustrating optimization and (e) healing of targeted gates in the S = 5 (≤29D optimization) configuration. Each hexagon corresponds to the cycle error for one pair (e_c,ij). Performant gates are blue, outliers are red, and unoptimized and targeted gates are gray.

Fig. 3. Optimization performance versus error mitigation strategy.

a CZXEB cycle error benchmarks (e_c, black boxes, left axis) and calibration failures (gray bars, right axis) for configurations optimized with all combinations of dephasing, relaxation, stray coupling, and frequency-pulse distortion error mitigation strategies activated (see lower matrix). The random baseline (red), outlier (orange), and crossover (green) standards are shown and their means are extended across the panel for comparison. b Idle frequency (f_i, first row), interaction frequency (f_ij, second row), and cycle error (e_c,ij, third row) heatmaps for the baseline standard with no mitigation strategies activated (first column), configurations with only one strategy activated (central columns), and the default configuration with all strategies activated (last column). As more mitigation strategies are progressively activated (from left to right in (a)), cycle errors and calibration failures trend downwards, highlighting the importance of metrology on the performance of our optimization strategy.

Fig. 4. Optimization scalability.

a Experimental and b simulated CZXEB cycle error benchmarks (e_c, boxes) in optimized (black) and unoptimized baseline (red) configurations of variable size. Simulated processors have size and connectivity corresponding to surface code logical qubits with distance d. The crossover standard (green), outlier standard (orange), and stitched configurations (purple) are shown for comparison. The solid lines are fits of the saturation model to the optimized (black) and baseline (red) benchmark means. Some boxes have been horizontally shifted to reduce overlap. In (a), N < 40 boxes combine benchmarks from multiple configurations to boost statistics. The x axis in (b) is linear in d with N = 2d² − 1 and the shaded region illustrates the experimentally accessible regime of our processor. c Benchmark heatmaps illustrating stitching of our N = 68 processor and (d) N = 1057 simulated processor. Outliers are not substantially amplified at seams (dashed lines), which is our primary concern. The dashed regions in (d) illustrate that stitching the d = 23 logical qubit with R = 4 is equivalent to stitching four d = 11 logical qubits.