The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors

Abstract

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3-B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

Keywords: 4-Transistor; CMOS image sensor; linear output range; operation conditions; pixel design.

Figure 5

The components of C_FD for all six channels, with red bare representing the SN capacitance extracted from the layout and blue bar representing the additional MOS capacitance.

Figure 1

An illustrative structure for a 4T pixel and its read-out circuit. The structures and circuit parameters investigated in this work are marked with a red circle.

Figure 2

(a) Photo of the test chip; (b) the basic diagram of the PCB, illustrating the fundamental structure of the test circuit.

Figure 3

The output of all six channels under the same illumination conditions. The cluster of curves for each channel contains data for 340 pixels.

Figure 4

Output of 100 frames from the left 640 pixels of a 20 μm pixel channel. At this point, to prevent saturation, the input light power that is adapted is relatively low. Pixels near the edge exhibit smaller output signals due to shadowing.

Figure 6

Relationship between C_FD and corresponding linear output range of each channel. Data are fitted for 10 μm and 20 μm pixels.

Figure 7

The linear output range of B3 to B6 channel with two types of PPD design with respect to C_FD (black line: PPD-SD; red line: PPD-LD). The blue dashed line is the increment in the linear output range for each channel.

Figure 8

Relationship between linear output range and TG sampling time for channels B4–B6. The C_FD values of the three channels show an approximately arithmetic progression.

Figure 9

(a) The output curve of 340 pixels for channel B6 under 3 different TG times: 0.4 μs, 1.6 μs and 7.2 μs respectively; (b) partial magnification of (a), providing a clearer illustration of the curves from the linear region to the nonlinear region.

Figure 10

Relationship between pixels linear output range and the Vdd of reset transistor.

Figure 11

Comparison of transfer curves for 10 μm pixels with and without an output buffer.

Figure 12

The read-out noise of 100 frames, averaged for 340 pixels under different conditions. (a) Readout noise for various TG times; (b) readout noise for PPD-SD and PPD-LD across four channels.

Figure 13

(a) The potential diagram of PPD-TG-FD structure during transfer process, where purple color represents the quantity of electrons within each area; (b) the style of output curve based on the potential diagrams given in (a).

Figure 14

1D model of a large-sized PPD for calculating charge transfer time.

Figure 15

Mathematical model of the charge transfer process. Electrons gradually diffuse from the region near the TG edge to the collection node. For ease of calculation, the diffusion process is divided into two stages: the first stage transfers half of the electrons in the PPD, and the second stage transfers the remaining half.