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. 2024 Jan 27;17(3):627.
doi: 10.3390/ma17030627.

Demonstration of 10 nm Ferroelectric Al0.7Sc0.3N-Based Capacitors for Enabling Selector-Free Memory Array

Li Chen  1 , Chen Liu  1 , Hock Koon Lee  1 , Binni Varghese  1 , Ronald Wing Fai Ip  1 , Minghua Li  1 , Zhan Jiang Quek  1 , Yan Hong  1 , Weijie Wang  1 , Wendong Song  1 , Huamao Lin  1 , Yao Zhu  1
Affiliations

Demonstration of 10 nm Ferroelectric Al0.7Sc0.3N-Based Capacitors for Enabling Selector-Free Memory Array

Li Chen et al. Materials (Basel). .

Abstract

In this work, 10 nm scandium-doped aluminum nitride (AlScN) capacitors are demonstrated for the construction of the selector-free memory array application. The 10 nm Al0.7Sc0.3N film deposited on an 8-inch silicon wafer with sputtering technology exhibits a large remnant polarization exceeding 100 µC/cm2 and a tight distribution of the coercive field, which is characterized by the positive-up-negative-down (PUND) method. As a result, the devices with lateral dimension of only 1.5 μm show a large memory window of over 250% and a low power consumption of ~40 pJ while maintaining a low disturbance rate of <2%. Additionally, the devices demonstrate stable multistate memory characteristics with a dedicated operation scheme. The back-end-of-line (BEOL)-compatible fabrication process, along with all these device performances, shows the potential of AlScN-based capacitors for the implementation of the high-density selector-free memory array.

Keywords: AlScN; FeRAM; capacitor; ferroelectric; selector-free memory array.

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Conflict of interest statement

The authors declare no conflicts of interest.

Figures

Figure 1
Figure 1
(a) Fabrication process flow and (b) structure of the 10 nm Al0.7Sc0.3N-based FeRAM device. (c) TEM image of the top electrode and AlScN stacks, confirming that the thickness of Al0.7Sc0.3N is 10 nm.
Figure 2
Figure 2
(a) Normalized capacitances of the devices with different sizes, showing size-independent behavior. The relative permittivity is extracted to be ~18. (b) DC currents of the devices with different sizes at ±4 MV/cm, showing size-independent behavior.
Figure 3
Figure 3
Non-PUND P-V curve of the 10 nm Al0.7Sc0.3N-based capacitor. The Pr value is due mainly to the leakage current.
Figure 4
Figure 4
(a) Schematic of the PUND method for characterizing the ferroelectricity of 10 nm Al0.7Sc0.3N film. Transient current response to the (b) “P” & “U” pulses and (c) “N” & “D” pulses. Ferroelectricity-induced switching current is clearly observed in “P” and “N” pulses. (d) Extracted Pr vs. pulse amplitude shows that 10 nm Al0.7Sc0.3N obtains Pr larger than 100 µC/cm2.
Figure 5
Figure 5
Heatmap of the on/off ratio and power consumptions with different pulse rise time and pulse amplitudes. (a,b) On/off ratio of the device using positive and negative pulses to read. Power consumption of the device under (c) positive switching and (d) negative switching operation modes. The power consumption of the device under optimal conditions is ~40 pJ. The size of measured device is 1.5 µm in diameter.
Figure 6
Figure 6
Transient response of the devices with different sizes. The size of device shows negligible impact on the on/off ratio.
Figure 7
Figure 7
Heatmap of the (a) on current, (b) off current, (c) on/off ratio, and (d) power consumption of the 5 × 4 selector-free array read at −6.5 V. The devices show good uniformity across the array. The white area refers to the short device, and the cell size is 1.5 µm in diameter. The letters “1”—“4” and “A”—“E” refer to the vertical and horizontal location of the devices in the array, respectively.
Figure 8
Figure 8
(a)Schematic of the selector-free array architecture based on ferroelectric FeRAM devices. (b) Schematic of measuring the current response after the Vp/2 (c) The transient current response of switching current after applying different numbers of Vp/2 pulses, showing no obvious degradation. (d) Extracted switching current and disturbance rate. The current remains the same level after applying numbers of Vp/2 pulses, and the disturbance rate is <2%.
Figure 9
Figure 9
(a) Endurance behavior of the FeRAM device. (b) The DC I-V curves of the device after cycling, showing that the negative leakage current increases while the positive leakage current decreases. (c) Schematic illustration of the reduced positive leakage current. (d) Retention behavior of on and off current states reading at −7 V shows up to 20,000 s in measurement and 10-year extrapolation with a high memory window.
Figure 10
Figure 10
(a) Multistate switching behavior of the devices via programming with different pulse amplitudes. Multiple states, such as “0”, “1”, “2”, and “3”, are achieved by applying pre-set pulse with pulse amplitudes of 0, 6.2, 7, and 8 V, respectively. (b) Statistic result of multistate behavior of the devices, showing the clear gap between each memory state.
See this image and copyright information in PMC

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