Multi-level, forming and filament free, bulk switching trilayer RRAM for neuromorphic computing at the edge

Abstract

CMOS-RRAM integration holds great promise for low energy and high throughput neuromorphic computing. However, most RRAM technologies relying on filamentary switching suffer from variations and noise, leading to computational accuracy loss, increased energy consumption, and overhead by expensive program and verify schemes. We developed a filament-free, bulk switching RRAM technology to address these challenges. We systematically engineered a trilayer metal-oxide stack and investigated the switching characteristics of RRAM with varying thicknesses and oxygen vacancy distributions to achieve reliable bulk switching without any filament formation. We demonstrated bulk switching at megaohm regime with high current nonlinearity, up to 100 levels without compliance current. We developed a neuromorphic compute-in-memory platform and showcased edge computing by implementing a spiking neural network for an autonomous navigation/racing task. Our work addresses challenges posed by existing RRAM technologies and paves the way for neuromorphic computing at the edge under strict size, weight, and power constraints.

Fig. 1. RRAM device stack and DC I-V switching characterization.

a Illustration of fabricated RRAM device stack and crossbar arrays. Bulk and filamentary RRAM switching mechanisms are compared. For bulk switching, the distribution of oxygen vacancies (V_O) is modulated between TiO_x and TiO₂ layers. For filamentary switching, the V_O filament formation and rupture occur near the bottom electrode. Scanning Electron Microscopy (SEM) images of fabricated b 16×16 crossbar array c single trilayer RRAM device, and d cross-section of a half-cut RRAM device. Filamentary switching characteristics of e S1 and f S2. g Coexistence of filamentary and bulk switching RRAM in S3. They show the opposite polarity due to the different resistance-switching mechanisms. Black arrows show the polarity of filamentary switching, while red arrows show polarity of bulk switching. h Bulk RRAM DC I-V characteristics of S4 without forming filaments. 50 cycles of DC sweeps perfectly overlap, showing highly uniform bulk switching.

Fig. 2. Cross-sectional analysis of bulk RRAM device.

a Cross-sectional bright-field Transmission Electron Microscopy (TEM) image of trilayer bulk RRAM. The bright contrast of TiO_x suggests a porous structure for the layer. b Atomic concentration profile measured by Scanning Transmission Electron Microscopy – Electron Energy Loss Spectroscopy (STEM-EELS) along the yellow arrow. All interfaces were determined based on the ion concentration and contrast in TEM image. The sputtered TiO_x layer shows a smaller oxygen concentration which is lower than ALD TiO₂ layer due to the V_O in the layer. c STEM-EELS mapping of red dotted box region in a.

Fig. 3. Electrical DC characterization of bulk RRAM devices.

a DC I-V switching curves of trilayer bulk RRAM with different diameter cells from 3 to 10 μm. b Double log plot of resistance vs. cell area. Area-scaling behavior with a slope of 1 suggests bulk switching of RRAM devices. Each size cell data is collected from 40 different devices measured at V_read = 0.1 V. c Cumulative distribution function (CDF) of bulk RRAM pristine resistance in different size cells. d CDF of LRS and HRS states programmed with DC sweep using bulk RRAM 5μm devices. e Band diagram of trilayer bulk RRAM. Al₂O₃ 3 nm wide gap layer acts as a tunneling barrier where the direct/Fowler-Nordheim (FN) tunneling happen at small/large voltage region. In the TiO_x layer, space-charge-limited-conduction (SCLC) occurs due to deep-level V_O defects. f Log(J/V²) vs. 1/V curves of high resistance state (HRS) and low resistance state (LRS). Both states show similar conduction mechanisms. g Log J – log V plot of LRS and HRS states. In low voltage regime, current density follows the Ohm’s law (J∝V), while it follows the Mark-Helfrich’s law (J∝V^m+1) in high voltage regime. h Trap density (N_t) vs. device resistance curve. N_t is achieved by the fitting the experimentally measured data with our electrical conduction model.

Fig. 4. Multilevel gradual switching characteristics of the bulk RRAM devices using pulse measurements.

a Multilevel switching using an identical pulse scheme for 32 different states. Set: −2.5 V, 500 μs/Reset: +1.5 V, 500 μs. b Multilevel switching using an identical pulse scheme for 32 different states. Set: −2.0 V, 5 ms/Reset: +1.0 V, 5 ms. c Multilevel switching using an incremental pulse scheme for 100 states. Set: −0.8 V to −2.78 V (−20 mV step)/Reset: +0.3 V to +0.993 V (+7 mV step). The transient current measurements using identical pulses d set (−2V) and e reset (+1.5 V) operations showing multi-level bulk switching without any abrupt current jumps (no filaments).

Fig. 5. Row-differential voltage sensing using neuromorphic compute-in-memory platform with packaged bulk RRAM crossbar.

a Row-differential scheme. Two RRAMs sharing the same column represent positive and negative weights by applying opposite polarity voltage to respective WLs. b Dynamic range for switching for bulk RRAM. c Dynamic range enhancement using the row-differential scheme. For 100 levels, the row-differential scheme can increase the effective dynamic range up to ~170. d Photograph of neuromorphic compute-in-memory board with packaged bulk RRAM crossbar. e Conventional current sensing using transimpedance amplifier. f Switched-capacitor voltage-sensing circuit to achieve higher energy efficiency. g Measured and expected MVM outputs for the differential encoding.

Fig. 6. Hardware implementation of SNN for a navigation/racing task.

a Examples of training and testing racetracks for navigation tasks. b Schematics of trained SNN (14 input/30 output neurons). c Weight map comparison between ideal weights and experimentally programmed weights on crossbars using the row-differential encoding. Two 16×16 crossbars were used for weight mapping. d Number of speed (Sp = 1, 1.6, 1.7) and steering angle (An = −0.23, 0, 0.17, 0.23) computations across navigation through all fifteen racetracks. Ideal software simulation and crossbar hardware implementation show highly consistent results. (Fitness score: 0.54 (Ideal S/W) vs. 0.43 (Crossbar H/W)). Ideal software vs. crossbar hardware computation of e steering angle and f speed during testing in the Catalunya map.