CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Abstract

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Keywords: CMOS; FDSOI; GAA; TFET; nanoscale transistors; process integration.

Figure 10

(a) New device structure for SOI FinFET [118] and (b) NC-FDSOI [119]. Reprinted with permission from ref. [118,119]. Copyright 2018 IEEE Publisher.

Figure 22

(a) TEM images of Si NS after replacement metal gate (RMG) [174], and (b) TEM images along the gate of the SiGe cladding layer [210]. Reprinted with permission from ref. [174,210]. Copyright 2017, 2020 IEEE Publisher.

Figure 43

Multiple-techniques approach to device metrology [405]. Reprinted with permission from ref. [405]. Copyright 2024, IEEE Publisher.

Figure 1

The process of VSAFETs, including the flow of selective qALE, and the flow and diagram of the Ni (Pt) silicide process. Reprinted with permission from ref. [9]. Copyright 2021 IEEE Publisher.

Figure 2

SEM micrographs: (a) epitaxially grown Si/SiGe/Si multilayers, (b) the tilted image of 3D nanostructure, (c) after qALE, (d) after inner spacer and sidewall spacer formation, (e) after silicide formation in structure wafer, and (f) TEM image after HKMG process. Reprinted with permission from ref. [9]. Copyright 2021 IEEE Publisher.

Figure 3

I_off–I_dsat data from transistors for with and without silicided pVSAFETs. Reprinted with permission from ref. [9]. Copyright 2021 IEEE Publisher.

Figure 4

High-resolution TEM micrograph with detailed information about energy-dispersive X-ray spectroscopy (EDX) analysis. The SiN dummy gate has been dry-etched followed by dHF for 60 s to stripe the oxide layer on the sidewall. Reprinted from ref. [11]. Copyright 2021 ACS Publisher.

Figure 5

(a) A schematic of an Fe-VSAFET, (b) STEM cross-section for Fe-VSAFET across AA′ direction, (c) STEM cross-section of channel region, (d) top view of STEM of a nanowire device, and (e) top view of a nanosheet device. Reprinted with permission from ref. [13]. Copyright 2021 IEEE Publisher.

Figure 6

Schematic of planar FDSOI transistor.

Figure 7

The typical cross-section TEM of an ultra-thin FDSOI device [66]. Reprinted with permission from ref. [66]. Copyright 2011 IOP Publishing.

Figure 8

(a) Top of the band schematic, (b) bulk CMOS currents leakage path. Reprinted with permission from ref. [68]. Copyright 2012 IEEE Publisher.

Figure 9

Schematic of body biasing in FDSOI.

Figure 11

The proposed NN-NEGF computation framework.

Figure 12

The proposed MOO framework couple with machine learning for 2D TMDC and black phosphorene FETs [139]. Reprinted with permission from ref. [139]. Copyright 2021 IEEE Publisher.

Figure 13

K1 factor evolution through the years of technological advancement.

Figure 14

A schematic picture of an EPE as tolerance for the relative placement of two edges (litho cut, via, and spacer feature).

Figure 15

SEG SiGe in source and drain (S/D) regions in different structures: (a) 2D planar [170], (b) 3D FinFETs [7] and (c) GAAFETs [169]. Reprinted from ref. [7,169,170]. Copyright Elsevier 2016, AIP 2013, and IEEE 2022 Publisher.

Figure 16

The I_ON/I_OFF ratio of FinFET PMOS fabricated with different S/D devices [175]. Reprinted with permission from ref. [175]. Copyright Springer 2019 Publisher.

Figure 17

TEM cross-section image and EDS element mapping of relatively defected SiGe growth layer [171]. Reproduced from ref. [171], open access by Springer, 2017.

Figure 18

Schematic diagram of the GeSn/Ge heterostructure growth and vertically stacked GAA NW FETs process [192]. Reprinted with permission from ref. [192]. Copyright 2021 ACS Publisher.

Figure 19

(a) Measured SS, (b) measured DIBL, and (c) simulated DIBL as a function of NW diameters [192]. Reprinted with permission from ref. [192]. Copyright 2021 ACS Publisher.

Figure 20

A schematic of a multilayer nanosheet GAA process sequence. (a) IS formation, and (b) CR process steps illustrated along dummy gate in x-direction, and along W_NS/“Fin” in y-direction [200]. Reprinted with permission from ref. [200]. Copyright 2021 IOP Publisher.

Figure 21

(a) X-ray diffraction reciprocal space mapping (XRD-RSM), (b) precession electron diffraction, and electron energy loss spectroscopy (EELS) of the SiGe/Si stack [174]. Reprinted with permission from ref. [174]. Copyright 2017 IEEE Publisher.

Figure 23

SEM cross-section micrographs of SiGe/Si multilayers after isotropic etching with reactant gas CF₄/O₂/He flow ratios of: (a) 1:0:0, (b) 1:1:0, (c) 4:1:0, and (d) 4:1:5 [253]. Reprinted with permission from ref. [253]. Copyright 2020 Springer Publisher.

Figure 24

Influence on etching profile due to CH₄ flow: (a) the dependence of vertical/lateral etch ratio and etch selectivity on CH₄ flow; (b) etching profile with no CH₄ flow; and with CH₄ flow of (c) 5 sccm; (d) 20 sccm; (e) and 30 sccm [255]. Reproduced from [255], open access by MDPI, 2020.

Figure 25

SEM micrographs of nanowires with diameter smaller than 20 nm after 100 cycles ALE using SiO₂ hard mask: (a) bird’s-eye top view; (b) 45° tilt top view; (c) cross-section image; (d) Si_0.72Ge_0.28 etching for different process time per cycle [260]. Reproduced from [260], open access by MDPI, 2020.

Figure 26

(a) Schematic illustration of a multilayer of Si_0.75Ge_0.25/Si nanowires applied for selective etching and TEM across image of 30 nm wide Si-Si_0.75Ge_0.25 nanowires after selective etching of Si (b) in TMAH 5% and (c) without the oxide–nitride hard mask 284. Reprinted with permission from ref. [279]. Copyright 2015, IOP Publisher.

Figure 27

Multilayer of nanosheet channel is released by applying HCl vapor [282]. Reprinted with permission from ref. [282]. Copyright 2017, IEEE Publisher.

Figure 28

Illustration of contact angle test of C1 and C8 (the straight-chain alkyl group in the agents has carbon numbers of 1 and 8, respectively) 297. Reprinted with permission from ref. [287]. Copyright 2017, IOP Publisher.

Figure 29

ATR-IR spectrum obtained from SiO₂ powder after C1 or C8 treatment demonstrates that C1 is better due to higher hydrocarbon groups around 750 to 900 cm⁻¹, whereas lower hydroxyl group is at 960 cm⁻¹ 297. Reprinted with permission from ref. [287]. Copyright 2017, IOP Publisher.

Figure 30

Top view micrographs of wafers after C1 and C8 treatment and drying 297. Reprinted with permission from ref. [287]. Copyright 2017, IOP Publisher.

Figure 31

Schematic pictures showing the integration flow of selective barrier in Cu interconnection [297]. Reprinted with permission from ref. [297]. Copyright 2021, IEEE Publisher.

Figure 32

(a) Schematics showing Cu reflow process. (b) Electromigration lifetime values for plated Cu vs. reflow Cu with Co liner at 32 nm pitch [299]. Reprinted with permission from ref. [299]. Copyright 2021, IEEE Publisher.

Figure 33

(a) Different oxide traps in FinFET illustrated in SILC spectrums, notated as oxide trap1 and oxide trap 2. (b) Typical positions of the interface traps as well as oxide traps created by HCD in a p- and n-type FinFET [321]. Reprinted with permission from ref. [321]. Copyright 2021, IEEE Publisher.

Figure 34

(a) Energy distribution of oxide traps in Si FinFETs for different NBTI stress time [323], reprinted with permission from ref. [323]. Copyright 2020, IEEE Publisher. (b) Energy distribution of oxide traps in Si FinFETs for different HCD stress time, and there are two generated oxide traps [324], reprinted with permission from ref. [324]. Copyright 2021, IEEE Publisher.

Figure 35

(a) NBTI-induced ΔV_th for different stress time measured at the low-T RMG pMOS processed w/o and w/H* − H₂ IL treatment at 25 °C and 125 °C [325], reprinted with permission from ref. [325]. Copyright 2021, IEEE Publisher. (b) Comparison of extrapolated lifetimes between baseline transistors and FGA-optimized ones [326], reprinted from ref. [326]. Open Access, 2021, IEEE Publisher.

Figure 36

(a) TEM image showing across the width of single nanosheet FET; (b) SEM image of a single vertical nanosheet after dry etch; (c) TEM image of a vertical nanowire resistor after TLM process step [333]. Reprinted with permission from ref. [333]. Copyright 2017, IEEE Publisher.

Figure 37

(a) Schematic image of a single NW MOSFET with GaSb channel where digital etching was used as the first step of the process; (b) SEM micrograph of a single NW transistor after defining the gate length; (c) transfer characteristics of the NW transistor with two-cycle DE- HCl:IPA 1:10 prior to high-κ deposition [336]. Reproduced from [336], open access by ACS, 2022.

Figure 38

Illustration of process fabrication using template-assisted selective deposition. (a) Schematic of the process flow: 1. Preparation of SOI wafer. 2. Patterning of the Si top layer and openings. 3. Etch-back of Si to create hollow SiO₂ template with a Si seed. 4. MOCVD of a p-i-n structure, the small arrow in the picture displays the growth direction. 5. Formed Ni/Au contacts. 6. Optical microscopy micrograph of a straight device and the coupler in the inset. (b) Top-view SEM micrograph of a straight device. (c) Top-view SEM image of a T-shape device displaying the FIB cut line. (d) Cross-section SEM micrograph of a T-shape device displaying an oxide-filled gap (with 50 nm width) separating the III–V-based active material and Si waveguide [342]. Reproduced from [342], open access by Springer Nature, 2022.

Figure 39

Three-dimensional schematic picture of a FinFET designed on GeSnOI wafer with multiple parallel fins [354]. Reproduced from [354], open access by OSA, 2018.

Figure 40

Three-dimensional schematic design of the integrated FETs on GeSnOI substrate [370].

Figure 41

(a) A scheme for electronic and photonic integration: (A) through Si vias, (B) bump bonding, (C) wire bonding [385]. Reproduced from [385], open access by Walter de Gruyter, 2014. (b) Intel’s integrated link contains fully integrated Si photonic transmitter chip with hybrid Si lasers (left side) and a fully integrated receiver chip based on Ge photodetectors (right side) [386]. Reprinted with permission from ref. [386]. Copyright 2010, Springer Nature Publisher.

Figure 42

Schematic drawing of carbon nano tube (CNT) analysis using deep learning-based Raman spectra measurement. (a) Employment of high-speed Raman to image a fork-like sample. (b) Piling up and finally generating an unlabeled Raman spectrum. (c) To classify the large, labeled datasets into the following categories: S-CNTs, MCNTs, and empty. (d) Using the deep learning model. (e) Organizing of individual spectra applying the model. (f) Identifying the CNTs [399]. Reproduced from [399], open access by Springer Nature, 2022.