Cross-architecture tuning of silicon and SiGe-based quantum devices using machine learning

Abstract

The potential of Si and SiGe-based devices for the scaling of quantum circuits is tainted by device variability. Each device needs to be tuned to operation conditions and each device realisation requires a different tuning protocol. We demonstrate that it is possible to automate the tuning of a 4-gate Si FinFET, a 5-gate GeSi nanowire and a 7-gate Ge/SiGe heterostructure double quantum dot device from scratch with the same algorithm. We achieve tuning times of 30, 10, and 92 min, respectively. The algorithm also provides insight into the parameter space landscape for each of these devices, allowing for the characterization of the regions where double quantum dot regimes are found. These results show that overarching solutions for the tuning of quantum devices are enabled by machine learning.

Figure 1

Device schematics. Si FinFET (a), GeSi nanowire (b) and Ge/SiGe heterostructure (c) device architectures and their corresponding current pinch-off hypersurfaces for hole transport calculated using a Gaussian process model for one of the tuning algorithm runs (d–f). Three gates are plotted for illustrative purposes with the remaining gates on each device set to a constant value. The bias was kept constant throughout the experiment. CATSAI was given control over the gate electrodes $V_1$–$V_4$, $V_1$–$V_5$, and $V_1$–$V_7$ on the FinFET, nanowire and heterostructure, respectively. The dashed white circles show the approximate locations of the quantum dots formed in the devices.

Figure 2

Outline of CATSAI’s workflow. The initialisation stage consists of setting $V_{\text{bias}}$ then measuring the maximum and minimum (offset) current flowing through the device. The sampling stage detects pinch-off locations in gate voltage space. The algorithm selects a vector in gate voltage space $\mathit{u}$ based on the model it generates of the hypersurface and of the probability of finding Coulomb peaks in a given location in gate voltage space. In the investigation stage the algorithm uses the plunger gates to sequentially acquire current traces and maps which are sent to the relevant classifiers. The Coulomb peak detector is a random forest classifier which determines whether Coulomb peaks are present (positive) or not (negative) within a current trace. In each iteration, the algorithm outputs a high-resolution current map if the double dot check score function is passed. After the investigation stage, the algorithm returns to the sampling stage.

Figure 3

Gate-voltage space exploration. Different charge carriers (gate operation modes) are represented in different columns (rows). Each panel illustrates the initial placement of the origin (white circle), search boundary (red cross), and search direction (black arrow). The gate voltage space is divided into regions of near-zero (blue) and non-zero (pink) current. Regions of voltage space which cannot be explored due to the gate voltage bounds set to avoid device damage are greyed out.

Figure 4

Device tuning. Examples of current map outputs on the different devices in which CATSAI was run. High resolution maps are generated during the investigation stage by sweeping the plunger gates of each device $V_{p1,p2}$; for the FinFET $V_{3,2}$ (a–c), the nanowire $V_{4,2}$ (d–f) and the heterostructure $V_{3,5}$ (g–i). These current maps are labelled a posteriori by humans to verify whether they correspond to the double quantum dot regime. C indicates the number of humans out of four who labelled the current map as corresponding to a double quantum dot regime. Red (blue) indicates regions of high (low) current in each map.

Figure 5

Benchmarking the algorithm’s performance. Cumulative sum of the average number of double quantum dot regimes verified by humans $\overline{C}$ (first and second columns) and probability of finding Coulomb peaks $\mathrm{P}(\mathrm{peaks})$ (third and fourth columns), as a function of laboratory time for each run of CATSAI and Random Search algorithms. Each coloured line corresponds to a different run. Rows correspond to the different devices. Only the first 4 h of each tuning run are shown for ease of visualisation. CATSAI outperforms Random Search in the number of double quantum dot regimes located for all devices. The value of $\overline{C}$ remains at 0 in many of the Random Search runs, and thus are not visible in the plots of $\overline{C}$ as a function of time. The increase in $\mathrm{P}(\mathrm{peaks})$ as a function of laboratory time observed for the CATSAI runs after the first 12 iterations can be explained by the algorithm ‘learning’ a better model of the hypersurface as the Gaussian process regression acquires more observations.

Figure 6

Double quantum dot regime volumes. Regions of voltage space (grey) encapsulate and define a volume where double quantum dots were found (black points) across all experimental runs of both random search and CATSAI in the FinFET (a), nanowire (b), and heterostructure (c). Three gates are plotted for illustrative purposes.