Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Abstract

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

Keywords: Artificial synapses; Dimension limits; Memory devices; Performance limits; Two-dimensional transistors.

Fig. 1

The limitations of traditional semiconductor materials and the merits of 2D TMDs for high performance electronic device. The diagram of flexible 2D FETs. Reproduced with permission. Reference [10] Copyright 2022, Springer Nature

Fig. 2

Demonstration of dimension and performance limits in 2D TMD transistors. Channel length diagram. Reproduced with permission. Reference [27] Copyright 2021, Springer Nature. Gate length diagram. Reproduced with permission. Reference [28] Copyright 2022, Springer Nature. Contact length diagram. Reproduced with permission. Reference [29] Copyright 2023, Springer Nature. Dielectric thickness diagram. Reproduced with permission. Reference [30] Copyright 2022, Springer Nature. Contact resistance diagram. Reproduced with permission. Reference [31] Copyright 2023, Springer Nature. Subthreshold swing diagram. Reproduced with permission. Reference [32] Copyright 2021, Springer Nature. Hysteresis loop diagram. Reproduced with permission. Reference [33] Copyright 2023, American Chemical Society. Carrier mobility diagram. Reproduced with permission. Reference [34] Copyright 2023, American Chemical Society. On/Off ratio diagram. Reproduced with permission. Reference [35] Copyright 2023, Springer Nature. P-type transistor diagram. Reproduced with permission. Reference [36] Copyright 2022, Wiley–VCH Verlag. Single-logic transistor diagram. Reproduced with permission. Reference [37] Copyright 2021, Springer Nature. Memory device diagram. Reproduced with permission. Reference [38] Copyright 2021, Springer Nature

Fig. 3

Comparison of conventional bulk material and 2D TMD material. a Bulk material. Reproduced with permission. Reference [1] Copyright 2022, Elsevier. b 2D TMD material. Reproduced with permission. Reference [39] Copyright 2011, Springer Nature

Fig. 4

Fabrication methods of monolayer TMDs. a Micromechanical exfoliation method. Reproduced with permission. Reference [51] Copyright 2022, Royal Society of Chemistry. b Chemical vapor deposition method. Reproduced with permission. Reference [47] Copyright 2022, Wiley

Fig. 5

Demonstration of the dimensions of 2D transistors, such as dielectric thickness, channel length, gate length, and contact length. a Top-gate transistor. b Back-gate transistor

Fig. 6

Scaling down the channel length of transistors. a 2D vertical-channel transistors. Reproduced with permission. Reference [65] Copyright 2020, Wiley. b Vertical transistor with a sub-1-nm channel. Reproduced with permission. Reference [27] Copyright 2021, Springer Nature. c Sub-2 nm vertical-channel transistors. Reproduced with permission. Reference [66] Copyright 2023, American Chemical Society. d Monolayer WSe₂ sloping-channel transistors. Reproduced with permission. Reference [67] Copyright 2023, American Chemical Society. e 2D fin field-effect transistors. Reproduced with permission. Reference [35] Copyright 2023, Springer Nature. f 2D devices with ultraflat sub-10 nm gap electrodes. Reproduced with permission. Reference [68] Copyright 2021, American Chemical Society. g Channel lengths of above 2D transistors

Fig. 7

Scaling down the gate length of transistors. a MoS₂ transistors with 1-nm gate lengths. Reproduced with permission. Reference [92] Copyright 2016, American Association for the Advancement of Science. b 1 T′/2H MoTe₂ FET with a CNT gate. Reproduced with permission. Reference [93] Copyright 2019, Springer Nature. c Vertical MoS₂ transistors with 0.34 nm monolayer graphene edge gate. Reproduced with permission. Reference [28] Copyright 2022, Springer Nature. d MoS₂ Transistor with 10-nm Si fin gate length. Reproduced with permission. Reference [96] Copyright 2019, Institute of Electrical and Electronics Engineers Inc. e Gate lengths of above 2D transistors

Fig. 8

Scaling down the contact length of transistors. a Ultrascaled contacts for monolayer MoS₂ FET. Reproduced with permission. Reference [109] Copyright 2023, American Chemical Society. b PtSe₂ FET with PtTe₂ edge contacts. Reproduced with permission. Reference [111] Copyright 2022, Elsevier. c MoS₂ transistors using in situ edge contacts. Reproduced with permission. Reference [112] Copyright 2019, American Chemical Society. d MoS₂ FET with single-walled-carbon-nanotube contacts. Reproduced with permission. Reference [29] Copyright 2023, Springer Nature. e MoS₂ FET with one-dimensional edge contacts. Reproduced with permission. Reference [113] Copyright 2019, American Chemical Society. f MoTe₂ FET with phase-transition contacts. Reproduced with permission. Reference [116] Copyright 2020, Wiley–VCH Verlag. g Contact lengths of above 2D transistors

Fig. 9

Scaling down the dielectric thickness of transistors. a Laser-writable high-k dielectric for van der Waals nanoelectronics. Reproduced with permission. Reference [129] Copyright 2019, American Association for the Advancement of Science. b The hybrid HfO₂/Sb₂O₃ dielectrics integrated on 2D MoS₂. Reproduced with permission. Reference [130] Copyright 2023, Springer Nature. c Bi₂O₂Se transistor with Bi₂SeO₅ dielectric nanosheets. Reproduced with permission. Reference [131] Copyright 2023, Springer Nature. d Back-gate MoS₂ four-probe FETs device. Reproduced with permission. Reference [132] Copyright 2023, Springer Nature. e MoS₂ back-gated FET with SrTiO₃ dielectric material. Reproduced with permission. Reference [30] Copyright 2022, Springer Nature. f MoS₂ FET with hybrid PTCDA/HfO₂ gate stack. Reproduced with permission. Reference [133] Copyright 2019, Springer Nature. g Bi₂O₂Se transistor with Bi₂SeO₅ dielectric nanosheets. Reproduced with permission. Reference [134] Copyright 2022, Springer Nature. h WSe₂ FET using 2D-BN dielectric interface. Reproduced with permission. Reference [150] Copyright 2019, Springer Nature. i Dielectric thickness of above 2D transistors. j Dielectric constants of above 2D transistors

Fig. 10

Contact resistance reduction of 2D transistors involves four strategies such as novel contact materials, doping engineering, interface engineering, and phase-change engineering. a The quantum limit in MoS₂ FET. Reproduced with permission. Reference [31] Copyright 2023, Springer Nature. b MoS₂ FET with semimetal (Bi) contacts. Reproduced with permission. Reference [156] Copyright 2021, Springer Nature. c Double-gate InSe FET. Reproduced with permission. Reference [171] Copyright 2023, Springer Nature. d WSe₂ FET with degenerately p-doped WSe₂ (Nb_0.005W_0.995Se₂) contacts. Reproduced with permission. Reference [172] Copyright 2016, American Chemical Society. e ZrTe₂-contacted MoS₂ transistor. Reproduced with permission. Reference [160] Copyright 2023, American Chemical Society. f Ideal spacer doping layer for 2D devices. Reproduced with permission. Reference [164] Copyright 2023, American Chemical Society. g MoTe₂ device with a 1 T'/2H phase homojunction. Reproduced with permission. Reference [173] Copyright 2015, American Association for the Advancement of Science. h 2D MoGe₂N₄ FET with Mxene contacts. Reproduced with permission. Reference [174] Copyright 2023, Royal Society of Chemistry. i WSe₂ FET with VSe₂ contact. Reproduced with permission. Reference [152] Copyright 2023, Springer Nature. j Contact resistance of above 2D transistors

Fig. 11

Subthreshold swing reduction of 2D transistors involves negative capacitance effect, resistive gate effect, tunnel effect, Dirac-source effect, and impact ionization effect. a MoS₂ NC-FET. Reproduced with permission. Reference [211] Copyright 2020, Wiley-Blackwell. b CIPS/MoS₂ vdW NC-FET. Reproduced with permission. Reference [212] Copyright 2019, Springer Nature. c MoS₂ NC-FET. Reproduced with permission. Reference [213] Copyright 2018, Springer Nature. d MoS₂/h-BN/graphene/CIPS vdW FeFET. Reproduced with permission. Reference [32] Copyright 2021, Springer Nature. e Atomic threshold switching MoS₂ FET. Reproduced with permission. Reference [214] Copyright 2021, Wiley–VCH Verlag. f MoS₂ TFET. Reproduced with permission. Reference [215] Copyright 2015, Springer Nature. g MoS₂/Graphene Dirac-source FET. Reproduced with permission. Reference [209] Copyright 2021, American Chemical Society. h Nanoscale vertical impact-ionization transistor. Reproduced with permission. Reference [207] Copyright 2020, American Chemical Society. i Subthreshold swings of above 2D transistors

Fig. 12

Hysteresis reduction of 2D transistors includes four strategies such as surface passivation, dielectric engineering, encapsulation, and post-fabrication treatments. a MoS₂ FET with hBN passivation layer. Reproduced with permission. Reference [238] Copyright 2015, Springer Nature. b MoS₂ FET with HfO_x dielectric. Reproduced with permission. Reference [239] Copyright 2022, Springer Nature. c MoS₂ negative-capacitance FET with h-BN/CuInP₂S₆ dielectric. Reproduced with permission. Reference [33] Copyright 2023, American Chemical Society. d Single-layer MoS₂ FET with post-fabrication treatment. Reproduced with permission. Reference [39] Copyright 2011, Springer Nature. e Hysteresis of above 2D transistors

Fig. 13

Carrier mobility enhancement in 2D transistors involves material quality improvement, surface functionalization, dielectric engineering, strain engineering, and device architecture optimization. a Rhombohedral-stacked bilayer WS₂ FET. Reproduced with permission. Reference [255] Copyright 2023, American Association for the Advancement of Science. b MoS₂ FET coupled with 2D organic frameworks. Reproduced with permission. Reference [256] Copyright 2023, Wiley-Blackwell. c CsPbBr₃ precipitation on a MoS₂ FET. Reproduced with permission. Reference [249] Copyright 2023, American Chemical Society. d MoS₂ FET with high dielectric constant of Bi₂SeO₂. Reproduced with permission. Reference [131] Copyright 2023, Springer Nature. e Dual-gate MoS₂ FeFET. Reproduced with permission. Reference [257] Copyright 2020, Wiley-Blackwell. f WSe₂ FET using conformal BN dielectric interface. Reproduced with permission. Reference [150] Copyright 2019, Springer Nature. g Crested two-dimensional transistors. Reproduced with permission. Reference [258] Copyright 2019, Springer Nature. h Strained MoS₂ transistor. Reproduced with permission. Reference [34] Copyright 2023, American Chemical Society. i MoS₂ transistor with air-gap structure. Reproduced with permission. Reference [151] Copyright 2023, Springer Nature. j Carrier mobilities of above 2D transistors

Fig. 14

Strategies to enhance the on/off ratio of 2D transistors involve gate engineering, contact optimization, defect control, device architecture optimization. a High-κ perovskite membranes as insulators for two-dimensional transistors. Reproduced with permission. Reference [30] Copyright 2022, Springer Nature. b Bi-contacted MoS₂ field effect transistors. Reproduced with permission. Reference [273] Copyright 2024, Science China Press. c High performance MoS₂ transistor fabricated via residue-free transfer. Reproduced with permission. Reference [191] Copyright 2023, Springer Nature. d Defect control for 2D transistors. Reproduced with permission. Reference [23] Copyright 2021, Springer Nature. e High performance MoS₂ transistor fabricated via modified chemical vapor deposition. Reproduced with permission. Reference [274] Copyright 2020, Springer Nature. f 2D fin field-effect transistors. Reproduced with permission. Reference [35] Copyright 2023, Springer Nature. g The on/off ratios of above 2D transistors

Fig. 15

P-type transistors. a NO₂ molecules for p-type dopants of WSe₂. Reproduced with permission. Reference [36] Copyright 2022, Wiley–VCH Verlag. b V-doped WSe₂ by mixing W with V precursors. Reproduced with permission. Reference [290] Copyright 2020, Wiley–VCH Verlag. c Ultrascaled p-type FET based on WSe₂/WO_xSe_y heterostructure. Reproduced with permission. Reference [291] Copyright 2023, American Chemical Society. d The p-type MoTe₂-based transistor fabrication. Reproduced with permission. Reference [176] Copyright 2023, Springer Nature. e The MoS₂/CNT heterojunction transistor. Reproduced with permission. Reference [292] Copyright 2023, Springer Nature. f WSe₂ FET after laser scanning. Reproduced with permission. Reference [285] Copyright 2019, American Chemical Society. g Atomic resolution images of Pt on multilayer WSe₂. Reproduced with permission. Reference [159] Copyright 2022, Springer Nature

Fig. 16

Single logic transistor. a Dual-gate MoS₂ transistor. Reproduced with permission. Reference [126] Copyright 2019, Springer Nature. b Dual-gate WSe₂ transistor. Reproduced with permission. Reference [297] Copyright 2022, Springer Nature. c Dual-gate WSe₂ transistor. Reproduced with permission. Reference [37] Copyright 2021, Springer Nature. d WSe₂ floating gate transistor. Reproduced with permission. Reference [298] Copyright 2023, American Chemical Society. e MoS₂ floating gate transistor. Reproduced with permission. Reference [299] Copyright 2020, Springer Nature. f Reconfigurable van der Waals ferroelectric transistor. Reproduced with permission. Reference [281] Copyright 2023, American Chemical Society

Fig. 17

Ultrafast memory devices. a The floating-gate memory device with atomically sharp interface. Reproduced with permission. Reference [308] Copyright 2021, Springer Nature. b Ultrafast semi-floating gate homojunctions. Reproduced with permission. Reference [314] Copyright 2023, Wiley-Blackwell. c Ultrafast flash memory based on van der Waals heterostructures. Reproduced with permission. Reference 38] Copyright 2021, Springer Nature. d Ultrafast MoS₂ floating memory. Reproduced with permission. Reference [315] Copyright 2022. e Ultrafast WSe₂ bipolar flash memory. Reproduced with permission. Reference [316] Copyright 2023, Springer Nature. f Ultrafast flash memory based on phase-engineered edge contacts. Reproduced with permission. Reference [82] Copyright 2015, Springer Nature. g Ultrafast van der Waals memory with PbI₂ as the charge trap layer. Reproduced with permission. Reference [313] Copyright 2023, Wiley-Blackwell. h Polarized Tunneling Transistor for Ultrafast Memory. Reproduced with permission. Reference [309] Copyright 2023, American Chemical Society. i Ultrafast flash memory based on a duplex two-dimensional material structure. Reproduced with permission. Reference [317] Copyright 2023, Springer Nature. j PZT-enabled MoS₂ floating gate transistor for ultrafast flash memory. Reproduced with permission. Reference [310] Copyright 2023, American Chemical Society