FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design

Abstract

In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal-semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (I_ON). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SS_AVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SS_AVG by 49% and achieves a superior I_ON/I_OFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Keywords: Forkshape; Gate ALL around (GAA); Heterojunction; Line tunneling; Metal–semiconductor interface; Nanosheet; Schottky barrier; Subthreshold swing (SS); Tunnel field-effect transistor (TFET).

Fig. 1

Schematic device structures of a the 3-D structure of Forkshape Inductive Tunnel Field-Effect Transistor (FS-iTFET), b the cross-sectional view of traditional PIN Nanosheet TFET (NS-TFET), c the cross-sectional view of Nanosheet Line-tunneling TFET (NS-LTFET), and d the cross-sectional view of single stack FS-iTFET for performance comparison. Where, the cutlines A–A’, C–C’, and E–E’ are set 1 nm under the Silicon Channel/HfO2 interface; the cutlines B–B’, D–D’, and F–F’ are set 5 nm next to the left Spacer/Silicon Channel interface

Fig. 2

Calibrations for a carrier transport, mobility, and quantum correction model [22], and b BTBT and SRH-TAT model [23]

Fig. 3

a–l Cross-sectional views of key fabrication process steps for FS-iTFET

Fig. 4

Performance comparison of NS-TFET, NS-LTFET, and FS-iTFET: a Transfer characteristics for different structures, b Corresponding subthreshold swing (SS) versus drain current, c Corresponding transconductance (gm) versus gate voltage, d SS behavior and I_ON/I_OFF comparison of different structures

Fig. 5

Energy band diagrams of NS-TFET, NS-LTFET, and FS-iTFET in different operational states: a, b Energy band diagrams of NS-TFET along cutlines A–A’ and B–B’, c, d Energy band diagrams of NS-LTFET along cutlines C–C’ and D–D’, e, f Energy band diagrams of FS-iTFET along cutlines E-E’ and D-D’

Fig. 6

Cross-sectional comparison of the electron band-to-band tunneling (BTBT) generation rate for NS-TFET, NS-LTFET, and FS-iTFET

Fig. 7

a Hole density along cutline I-I’ in a FS-iTFET, b Electric field diagram along the silicon channel for NS-LTFET and FS-iTFET, respectively

Fig. 8

a Transfer characteristics of FS-iTFET with different Schottky Barrier Heights (SBH), b Corresponding subthreshold swing (SS) versus drain current, c Corresponding hole density along cutline I-I’, and d Corresponding band diagram along cutline I-I’

Fig. 9

a Transfer characteristics of FS-iTFET with different channel/source materials, b Corresponding subthreshold swing (SS) versus drain current

Fig. 10

a Transfer characteristics of FS-iTFET with and without inner oxide between the source/drain region, b-1 Cross-sectional view of FS-iTFET with inner oxide between the source/drain region, b-2 Cross-sectional view of FS-iTFET without inner oxide between the source/drain region, c, d Energy band diagram of NS-TFET in the OFF-state along cutlines G–G’ and H–H’. Where the cutlines G–G’ and H–H’ are set 1 nm below the silicon channel/germanium source interface

Fig. 11

Electron band-to-band tunneling (BTBT) generation rate of FS-iTFET with and without inner oxide between the source/drain region

Fig. 12

a Transfer characteristics of FS-iTFET with interface trap density (N_it) between Si/Ge, comparing different models, b Transfer characteristics of FS-iTFET with varying N_it between Si/Ge, c Transfer characteristics of FS-iTFET with N_it between Si/Ge, comparing different temperatures, d Corresponding subthreshold swing (SS) versus drain current at different temperatures

Fig. 13

a Transfer characteristics of the corresponding device structure with interface traps between heterojunctions, b Corresponding subthreshold swing (SS) versus drain current, c Impact of interface traps between heterojunctions on I_ON in different structures, d Impact of interface traps between heterojunctions on I_OFF in different structures

Fig. 14

Benchmark comparison of the I_ON/I_OFF ratio and average subthreshold swing (SS_avg) of our devices with those proposed in other papers

Fig. 15

Impact of subband quantum confinement effect (QCE) on FS-iTFET: a Transfer characteristics of FS-iTFET with and without subband QCE, b Corresponding subthreshold swing (SS) versus drain current

Fig. 16

Impact of channel/source thickness on FS-iTFET: a Transfer characteristics of FS-iTFET for different channel/source thicknesses, b Corresponding subthreshold swing (SS) versus drain current