A Wireless Artificial Mechanoreceptor in 180-nm CMOS

Abstract

This article presents an implantable low-power wireless integrated system for tactile sensing applications. The reported ASIC utilizes a low-loss magnetic human body communication channel for both wireless power and data transfer. The chip is hybrid-integrated with an in-house fabricated MEMS capacitive force sensor to form an implantable artificial mechanoreceptor. An on-chip correlated double sampling capacitance to time converter consumes 750nW from a 1.2V on-chip regulated supply, achieving a 2.0fF resolution for an input capacitance of 14pF and a FoM of 49 fJ/c-s while occupying an area of only 0.04 mm². The capacitance to time converter has a time-multiplexed mode to interface with 4 input capacitors. Wireless power management feedback is utilized to ensure robust operation in the presence of hand gesture changes and process-voltage-temperature variations. The on-chip data transmitter can operate in on-off keying or frequency-shift keying modulation formats, where it consumes only 7.8 $\mu \text{W}$ in the on-off keying mode. The 1.62mm² chip is fabricated in a standard 180nm CMOS process and consumes 110.3 $\mu \text{W}$ .

Keywords: Body channel communication (BCC); capacitance to time converter (CTC); correlated double sampling (CDS); energy efficiency; magnetic human body communication (mHBC); power management; sensor interface.

Fig. 1.

(a) Different tactile sensing mechanism used to restore somatosensation, and (b) proposed implantable tactile sensing system.

Fig. 2.

(a) Receiving coil. (b) The mHBC channel loss characterization, where the maximum available gain from the wrist to the implant location were measured for different hand gestures and receiver locations.

Fig. 3.

Block diagram of the proposed implantable artificial mechanoreceptor.

Fig. 4.

Circuit schematic of the on-chip power management unit and device sizes (start-up circuit for the bandgap reference is not shown).

Fig. 5.

Layout of devices M₁, M₂, D₁ and D₂ in the rectifier.

Fig. 6.

Simulated power conversion efficiency of the voltage doubler rectifier for (a) different input power and load resistances, and (b) different input power and process corners.

Fig. 7.

Simulated and measured regulator outputs for different input voltages.

Fig. 8.

Schematic of the clock generator and its output frequencies.

Fig. 9.

Measured temperature response from 5 samples of the proposed relaxation oscillator and post-layout simulated response with (black) and without (blue) temperature compensation.

Fig. 10.

(a) Schematic of the correlated double sampling capacitance to time converter. (b) Timing diagram of the CTC. (c) Time-multiplexed mode enabling the CTC to interface with a capacitive shear force sensor.

Fig. 11.

Measured CTC output, standard deviation (×1000), and oscillation frequency for different input capacitors. Note that standard deviation is calculated from averaged output capacitance in 1 ms sampling windows.

Fig. 12.

Measurement results from 15 chips: (a) on-chip quantized CTC output and (b) CTC oscillation frequency.

Fig. 13.

Temperature response of the CTC output quantized using the on-chip quantizer.

Fig. 14.

System timing diagram of IAM1.

Fig. 15.

Simplified schematic of the data hub and transmitter.

Fig. 16.

Chip microphotographs for (a) IAM1, and (b) IAM2.

Fig. 17.

Chip power breakdown for (a) IAM1, and (b) IAM2.

Fig. 18.

Wireless test set-up.

Fig. 19.

Wirelessly received chip outputs for IAM1 in (a) OOK mode, and (2) FSK mode.

Fig. 20.

Human body demonstration for the proposed (a) IAM1, and (b) IAM2, both configured in the single input channel mode.

Fig. 21.

Schematic of the proposed capacitive force sensor.

Fig. 22.

Sensor fabrication process. (a) wafer cleaning and Ti/Cu seed layer deposition; (b) lithography patterned mold for pads; (c) electroplate pads; (d) ablate feedthroughs using excimer laser; (e) electroplate feedthrough vias; (f) Ti deposition; (g) lithography patterned photoresist; (h) RIE etching cavity; (i) spray coating; (j) lithography patterned photoresist; (k) Ti deposition; (l) localized fusion bonding.

Fig. 23.

Fabricated silica-based capacitive sensor prototype.

Fig. 24.

Sensor characterization using the proposed interface IC for (a) fixed force load, and (b) dynamic force load.