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Review
. 2023 Dec 29;4(6):1431-1441.
doi: 10.1016/j.fmre.2023.10.020. eCollection 2024 Nov.

The Big Chip: Challenge, model and architecture

Yinhe Han  1   2   3 , Haobo Xu  1 , Meixuan Lu  1   2 , Haoran Wang  1   2 , Junpei Huang  1   4 , Ying Wang  1   2 , Yujie Wang  1   2   3 , Feng Min  1 , Qi Liu  5 , Ming Liu  5 , Ninghui Sun  1   2
Affiliations
Review

The Big Chip: Challenge, model and architecture

Yinhe Han et al. Fundam Res. .

Abstract

As Moore's Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maximum reticle area, cost, and manufacturing yield, the chip's area cannot be continuously increased, and it encounters what is known as the "area-wall". In this paper, we provide a detailed analysis of the area-wall and propose a practical solution, the Big Chip, as a novel chip form to continuously improve performance. We introduce a performance model for evaluating Big Chip and discuss its architecture. Finally, we derive the future development trends of the Big Chip.

Keywords: Area-wall; Big Chip; Chiplet; Integrated chips; Performance model.

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Conflict of interest statement

The authors declare that they have no conflicts of interest in this work.

Figures

Fig. 1
Fig. 1
Demonstration of lithography system.
Fig. 2
Fig. 2
Maximal critical area (mm2) that can be manufactured under yield constraints. Left part and right part showing 5 nm and 14 nm processings respectively. The horizontal dashed line shows the 858 mm2 physical monolithic die area upper bound.
Fig. 3
Fig. 3
Cost per transistor when implementing different critical area (mm2) of 5 nm (left) and 14 nm (right) processing nodes. The cost is normalized to the cost of smallest monolithic die plotted.
Fig. 4
Fig. 4
System cost (arbitrary unit) when implementing different critical area (mm2) of 5 nm (left) and 14 nm (right) processing nodes.
Fig. 5
Fig. 5
The fabrication and packaging comparison of chiplet integration and wafer-scale integration, . (a) Wafer-scale integration. (b) Chiplet integration.
Fig. 6
Fig. 6
The chiplet IP reuse scheme.
Fig. 7
Fig. 7
Three possible trends of performance model.
Fig. 8
Fig. 8
The comparison of performance models of chiplet, monolithic multi-core and multi-chip systems.
Fig. 9
Fig. 9
The comparison between the performance models of 2D-integration and 3D-stacking designs of Tetris. The 3D-stacking optimization changes the shape of the model curve.
Fig. 10
Fig. 10
The impacts ofαoff−chipandαintra−chip.
Fig. 11
Fig. 11
The architecture of the Big Chip processor. (a) Symmetric-chiplet Architecture. (b) NUMA-chiplet Architecture. (c) Cluster-chiplet Architecture. (d) Heterogeneous-chiplet Architecture. (e) Hierarchal-chiplet Architecture.
Fig. 12
Fig. 12
Comparison between different architectures of Big Chip.
Fig. 13
Fig. 13
Zhejiang Big Chip overview.
See this image and copyright information in PMC

References

    1. Shao Y.S., Clemons J., Venkatesan R., et al. Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. 2019. Simba: Scaling deep-learning inference with multi-chip-module-based architecture; pp. 14–27.
    1. Moore G.E. Cramming more components onto integrated circuits, reprinted from electronics, volume 38, number 8, april 19, 1965, pp. 114 ff. IEEE Solid-State Circuits Soc. Newsl. 2006;11(3):33–35.
    1. Dennard R.H., Gaensslen F.H., Yu H.-N., et al. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits. 1974;9(5):256–268.
    1. Lau J.H. Springer Nature; 2021. Semiconductor Advanced Packaging.
    1. Neumann J.T., Gräupner P., Kaiser W., et al. Photomask Technology 2012. vol. 8522. SPIE; 2012. Interactions of 3D mask effects and NA in EUV lithography; pp. 322–333.

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