Brain-like hardware, do we need it?

Abstract

The brain's ability to perform efficient and fault-tolerant data processing is strongly related to its peculiar interconnected adaptive architecture, based on redundant neural circuits interacting at different scales. By emulating the brain's processing and learning mechanisms, computing technologies strive to achieve higher levels of energy efficiency and computational performance. Although efforts to address neuromorphic solutions through hardware based on top-down CMOS-based technologies have obtained interesting results in terms of energetic efficiency improvement, the replication of brain's self-assembled and redundant architectures is not considered in the roadmaps of data processing electronics. The exploration of solutions based on self-assembled elemental blocks to mimic biological networks' complexity is explored in the general frame of unconventional computing and it has not reached yet a maturity stage enabling a benchmark with standard electronic approaches in terms of performances, compatibility and scalability. Here we discuss some aspects related to advantages and disadvantages in the emulation of the brain for neuromorphic hardware. We also discuss possible directions in terms of hybrid hardware solutions where self-assembled substrates coexist and integrate with conventional electronics in view of neuromorphic architectures.

Keywords: CMOS; hardware; nanoparticle networks; neuromorphic; perceptron; unconventional computing.

Figure 1

On the left, dendritic tree of pyramidal neurons from cortical layer 2 and 3, featured by two distinct domains, i.e., the basal and the apical dendrites, adapted from Spruston (2008); on the right, connectome from human brain, adapted from Carving Out Brain Structure with Connectomics (2022).

Figure 2

Neuron model proposed by Neumann (1956) (A), and the organization of the perceptron proposed by Rosenblatt (1958) (B).

Figure 3

Schematic representation of cluster-assembled thin film deposition: (A) two or multi metallic electrodes are deposited on a flat and insulating substrate, (B) a mask is placed between the clusters beam and the sample for its negative printing on the substrate, (C) the mask is removed and a nanostructured film with rough and disordered structure (D) is formed.

Figure 4

Schematic representation of multielectrode device based on nanostructured random-assembled material, implementing a Boolean functions classifier according to the Receptron model. The Boolean function is obtained by thresholding the analog outputs recorded at low voltage (lower than 1 V) for all the possible combinations of the 3-bit inputs. By applying a short pulse of a voltage highest than a certain threshold between a pair of electrodes, the connectivity of the network changes and a new conductance map is written. After this stochastic writing process, a new sequence of analog outputs is recorded, by implementing a different Boolean function.