A 6.7 μW Low-Noise, Compact PLL with an Input MEMS-Based Reference Oscillator Featuring a High-Resolution Dead/Blind Zone-Free PFD

Abstract

This article reports a 110.2 MHz ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications. It utilizes a 6.89 MHz MEMS-based oscillator as an input reference. An ultra-low-power, high-resolution phase-frequency detector (PFD) is utilized to achieve low-noise performance. Eliminating the reset feedback path used in conventional PFDs leads to dead/blind zone-free phase characteristics, which are crucial for low-noise applications within a wide operating frequency range. The PFD operates up to 2.5 GHz and achieves a linear resolution of 100 ps input time difference (Δtin), without the need for any additional calibration circuits. The linearity of the proposed PFD is tested over a phase difference corresponding to aa Δtin ranging from 100 ps to 50 ns. At a 1 V supply voltage, it shows an error of <±1.6% with a resolution of 100 ps and a frequency-normalized power consumption (Pn) of 0.106 pW/Hz. The PLL is designed and fabricated using a TSMC 65 nm CMOS process instrument and interfaced with the MEMS-based oscillator. The system reports phase noises of -106.21 dBc/Hz and -135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. It consumes 6.709 μW at a 1 V supply and occupies an active CMOS area of 0.1095 mm².

Keywords: frequency synthesizer; high resolution; low noise; microelectromechanical system (MEMS); oscillator; phase-frequency detector (PFD); phase-locked loop (PLL); time difference; timing; ultra-low power.

Figure 1

The PLL system with its MEMS-based input reference oscillator.

Figure 2

MEMS -based oscillator: (a) system block diagram; (b) measured MEMS electrical transmission (S21); (c) extracted RLC electrical equivalent linear model; (d) TIA circuit design.

Figure 3

A simplified diagram of the PLL (a) ring-based VCO and (b) $N=16$ divider.

Figure 4

(a) Standard current-based and (b) charge transfer-based CPs.

Figure 5

(a) A PFD state machine. (b) Traditional tri-state PFD block and (c) timing diagrams.

Figure 6

Circuit diagram of the proposed PFD.

Figure 7

Proposed PFD: (a) transfer curve; (b) Monte Carlo histograms (N = 500) of the $UP$ output at $\Delta t_{in}$ = 1 ns.

Figure 8

Error under PVT variations.

Figure 9

(a) Fabricated die micrograph; (b) photograph of the testing board used to test the PFD.

Figure 10

$REF$ leads $FB$: (a) $\Delta t_{in}$ = 125 ns; (b) $\Delta t_{in}$ = 470 ns.

Figure 11

$REF$ lags $FB$: (a) $\Delta t_{in}$ = −125 ns; and (b) $\Delta t_{in}$ = −470 ns.

Figure 12

Stand-alone PFD validation: (a) picture of the actual setup; (b) setup block diagram.

Figure 13

Measured PFD error compared to simulation.

Figure 14

Measured phase noise at a 110.2 MHz output frequency.

Figure 15

Breakdown of the power consumption of the system at a 110.2 MHz output frequency.

Figure 16

(a) Picture of the wire-bonded dies in the package. (b) Zoomed-in view of the MEMS device wire-bonded to the CMOS die, forming the system. (c) Photograph of the testing board used to test the system.