The Overview of Silicon Carbide Technology: Status, Challenges, Key Drivers, and Product Roadmap

Abstract

Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

Keywords: SiC MOSFET; SiC technology; automotive industry; battery electric vehicles.

Figure 1

An example of the SiC MOSFET manufacturing process flow.

Figure 2

Epitaxial layer growth.

Figure 3

SOITEC’s Smart Cut SiC wafer manufacturing process. Reproduced with permission from [5].

Figure 4

Activation ratio vs. temperature dependence (a) and resistivity of the region obtained during implantation at RT and at the elevated temperature (b). Reproduced with permission from [7].

Figure 5

Incomplete ionization ratio calculated using theoretical model at elevated temperatures (solid line) compared to parameterization of empirical data (dashed). Reprinted from [40], with permission from AIP Publishing.

Figure 6

Dependence between Vbr and implantation dose which was used for single-zone JTE fabrication. A dose of zero corresponds to the structures without JTE. Experimental points are shown as individual marks; the curves were obtained by simulation with various effective surface charges.

Figure 7

The 4H-SiC substrate with a SiO₂ mask.

Figure 8

Selectivity of SiC etching over SiO₂ in SF₆ + O₂ plasma as a function of (a) the plasma P_RIE power at p = 30 mTorr and (b) the plasma pressure at P_RIE = 250 W.

Figure 9

SEM image of the MESA structure obtained in the course of the RIE of 4H-SiC (at P_RIE—300 W; O₂ flowrate—30 sccm; SF₆ flowrate—20 sccm; and p—30 mTorr). The height of this MESA structure was around 1.35 µm.

Figure 10

SEM images of MESA structures obtained after the ICP-RIE of SiC with the Cr mask in the SF₆ plasma (no micro-trenching effect on the MESA sidewall is visible) performed with an magnification of (a) 220× (b) 1000× (c) 7000×. The etching process parameters were SF₆ flowrate = 100 sccm, P_RIE = 50 W, P_ICP = 2500 W, p = 7 mTorr, and t = ~18.5 min (a time of the total Cr mask etching).

Figure 11

Images of the SiC surface after ICP-RIE processes with two different types of masks: (a) the aluminum mask and (b) the AZ 4562 photoresist.

Figure 12

SEM images of SiC MESA structures after the ICP-RIE of SiC with photoresist AZ 4562 mask, with various RIE powers: (a) 100 W, (b) 200 W, and (c) 300 W. The pressure in the reactor was 7 mTorr and the ICP power was 800 W. The gas flowrates: SF₆—18 sccm; O₂—9 sccm.

Figure 13

SEM images of SiC structures after the ICP-RIE of SiC with photoresist AZ 4562 mask, with various ICP powers: (a) 800 W and (b) 1300 W. The pressure in the reactor was 7 mTorr and the RIE power was 100 W. The gas flowrates: O₂—9 sccm; SF₆—18 sccm.

Figure 14

SiC trenches obtained after ICP-RIE in pure SF₆ plasma (photos at the top; P_ICP = 2250 W, P_RIE = 50 W, p = 7 mTorr, gas flowrate SF₆ = 100 sccm) and in SF₆ + 50% O₂ (photos at the bottom; P_ICP = 2250 W, P_RIE = 50 W, p = 7 mTorr, gas flowrates: SF₆ = 50 sccm and O₂ = 50 sccm). (a,d) View of the structure profile; (b,e) SiC surface morphology; (c,f) view of sidewalls with the inclination angles of ~90° and ~63°, respectively.

Figure 15

Typical energy distribution of trap state densities across the 4H-SiC bandgap for samples produced in dry oxidation.

Figure 16

Identified defects in the 4H-SiC–SiO₂ interface contributing to the active trap profile: <1> without stacking fault and <2> with stacking fault. Based on [88,92,94].

Figure 17

Trap density profiles calculated by the Hi-Lo method (100 kHz) near the conduction band edge of 4H-SiC (0001). (a) Black diamonds—simple dry oxidation at 1175 °C; green triangles—a simple dry oxidation followed by the 1000 °C NO annealing step. (b) Black diamonds—simple dry oxidation at 1175 °C; brown squares—a simple dry oxidation followed by the POCl₃ annealing and subsequent NO annealing step at 1000 °C; green triangles—a simple dry oxidation followed by the 1000 °C NO annealing step for comparison. Dashed lines—a fitted U-shaped profile (U6) for each sample. Based on [106].

Figure 18

Scheme of first-generation SiC power modules. TIM1 at chip—DBC interface; TIM2 at DBC—radiator interface.

Figure 19

Flex printed circuit board solution (SKIN).

Figure 20

Direct Lead Bonding (DLB) structure.

Figure 21

Package with double-sided cooling.