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. 2024 Dec 24;25(1):33.
doi: 10.3390/s25010033.

A Novel Real-Time Threshold Algorithm for Closed-Loop Epilepsy Detection and Stimulation System

Liang-Hung Wang  1 , Zhen-Nan Zhang  1 , Chao-Xin Xie  1 , Hao Jiang  1 , Tao Yang  1 , Qi-Peng Ran  1 , Ming-Hui Fan  1 , I-Chun Kuo  2 , Zne-Jung Lee  3 , Jian-Bo Chen  4 , Tsung-Yi Chen  5 , Shih-Lun Chen  6 , Patricia Angela R Abu  7
Affiliations

A Novel Real-Time Threshold Algorithm for Closed-Loop Epilepsy Detection and Stimulation System

Liang-Hung Wang et al. Sensors (Basel). .

Abstract

Epilepsy, as a common brain disease, causes great pain and stress to patients around the world. At present, the main treatment methods are drug, surgical, and electrical stimulation therapies. Electrical stimulation has recently emerged as an alternative treatment for reducing symptomatic seizures. This study proposes a novel closed-loop epilepsy detection system and stimulation control chip. A time-domain detection algorithm based on amplitude, slope, line length, and signal energy characteristics is introduced. A new threshold calculation method is proposed; that is, the threshold is updated by means of the mean and standard deviation of four consecutive eigenvalues through parameter combination. Once a seizure is detected, the system begins to control the stimulation of a two-phase pulse current with an amplitude and frequency of 34 μA and 200 Hz, respectively. The system is physically designed on the basis of the UMC 55 nm process and verified by a field programmable gate array verification board. This research is conducted through innovative algorithms to reduce power consumption and the area of the circuit. It can maintain a high accuracy of more than 90% and perform seizure detection every 64 ms. It is expected to provide a new treatment for patients with epilepsy.

Keywords: ASIC; closed loop; electrical stimulation; epilepsy detection; feature extraction.

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Conflict of interest statement

The authors declare no conflicts of interest.

Figures

Figure 1
Figure 1
Diagram of the system.
Figure 2
Figure 2
Threshold solution process.
Figure 3
Figure 3
Block diagram of digital circuit.
Figure 4
Figure 4
SPI interface data flow.
Figure 5
Figure 5
State control flowchart.
Figure 6
Figure 6
Circuits of the feature detection module, including four comparators (i.e., C1, C2, C3, andC4), and eight AND gates (i.e., A1, A2,…, and A8) and one OR gate (i.e., O1).
Figure 7
Figure 7
Circuits of the feature calculation module.
Figure 8
Figure 8
Threshold calculation.
Figure 9
Figure 9
One pulse stimulation cycle.
Figure 10
Figure 10
Block diagram design of the stimulation module (The red dotted lines are submodules).
Figure 11
Figure 11
FPGA test results.
Figure 12
Figure 12
Integral digital layout.
Figure 13
Figure 13
Simulation results of proposed circuit.
Figure 14
Figure 14
Digital analog hybrid simulation.
See this image and copyright information in PMC

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