Recent advances in CMOS-compatible synthesis and integration of 2D materials

Abstract

The upcoming generation of functional electronics in the era of artificial intelligence, and IoT requires extensive data storage and processing, necessitating further device miniaturization. Conventional Si CMOS technology is struggling to enhance integration density beyond a certain limit to uphold Moore's law, primarily due to performance degradation at smaller dimensions caused by various physical effects, including surface scattering, quantum tunneling, and other short-channel effects. The two-dimensional materials have emerged as highly promising alternatives, which exhibit excellent electrical and mechanical properties at atomically thin thicknesses and show exceptional potential for future CMOS technology. This review article presents the chronological progress made in the development of two-dimensional materials-based CMOS devices with comprehensively discussing the advancements made in material production, device development, associated challenges, and the strategies to address these issues. The future prospects for the use of two-dimensional materials in functional CMOS circuitry are outlooked, highlighting key opportunities and challenges toward industrial adaptation.

Keywords: 2D materials; CMOS devices; Flexible electronics; M3D integration; TMDs.

Fig. 1

Merits of 2D materials over conventional bulk materials toward the development of ultra-scaled electronic devices. a Schematic representations of the bulk semiconductor and 2D materials. Corresponding merits and de-merits are highlighted below. Schematic representation of the typical MOS-FET structure. The band diagram of the long- and short-channel FETs showing the drain-induced barrier lowering (DIBL) occurring in bulk semiconductors-based MOS-FETs. Reproduced with permission [10]. Copyright 2022, Elsevier. b Carrier mobility of various representative channel materials including bulk Si, Ge, and various 2D materials (left panel). The right panel shows the on-current levels of FETs fabricated with various TMDs. Reproduced with permission [9]. Copyright 2022, Springer Nature

Fig. 2

Roadmap showing the chronological development of 2D materials-based CMOS devices. From left to right; Microscopic image of a single thin film transistor fabricated with exfoliated MoS₂ flake. Reproduced with permission [4]. Copyright 2011, Springer Nature. Optical image of an integrated circuit fabricated with mechanically exfoliated single-layer MoS₂. The developed device consists of two nearby designed transistors controlled with HfO₂ gate dielectric. Reproduced with permission [21]. Copyright 2011, American Chemical Society. Image of the NAND gate and the SRAM devices fabricated with exfoliated bilayer MoS₂. Both of the devices were designed on the same MoS₂ flake. Reproduced with permission [20]. Copyright 2012, American Chemical Society. FET arrays fabricated with CVD-grown large are MoS₂. Reproduced with permission [19]. Copyright 2015, Springer Nature. CVD-grown TMDs-based flexible logic circuits. Reproduced with permission [18]. Copyright 2016, Wiley–VCH GmbH. CVD-grown MoS₂-based FETs array and inverters. The two n-type transistors were integrated together to realize an inverter. Reproduced with permission [17]. Copyright 2016, Springer Nature. The microprocessor developed with MOCVD grown large are MoS₂ films. Reproduced with permission [16]. Copyright 2017, Springer Nature. Integration of multistage MoS₂ transistors to realize various logic devices such as inverters, NOR-, NAND-gates, AND-gates, ring oscillators, and SRAMs over large area flexible substrates. Reproduced with permission [15]. Copyright 2020, Springer Nature. Development of wafer scale integrated circuits over a 2-inch MoS₂ wafer. Reproduced with permission [14]. Copyright 2021, Springer Nature. 2D materials based flexible M3D device. Reproduced with permission [13]. Copyright 2023, Springer Nature. M3D electronics CMOS electronics developed with combining 2D materials based n- and p-type FETs in vertical architecture. Reproduced with permission [12]. Copyright 2024, Springer Nature

Fig. 3

Synthesis of p- and n-type 2D semiconductors for CMOS electronics. a Schematic representation of a typical CVD system. b CVD growth mechanism for synthesizing the 2D atomic layers and optical microscopic images of various monolayer TMD crystals synthesized using the CVD approach. Reproduced with permission [62]. Copyright 2018, Springer Nature. c Schematic diagram representing a typical MOCVD growth chamber generally utilized to grow the wafer scale TMDs. A precise flow of metal–organic and chalcogen percusses is inserted into the growth chamber using mass flow controllers. d Photographic images of MoS₂ and WS₂ monolayers synthesized on fused silica substrates. The right image shows the patterned MoS₂ film after transferring it to a 4-inch SiO₂/Si substrate. Reproduced with permission [19]. Copyright 2015, Springer Nature. e Photograph of n-type monolayer TMDs, MoS₂ and WS₂, grown on 6-inch quartz wafers and a batch of n-channel TFT arrays fabricated with grown MoS₂ over a large area. The right panel shows the transfer curves of 900 FETs having channel width and channel length of 50 μm, and 10 μm, respectively. Reproduced with permission [75]. Copyright 2020, Wiley‐VCH GmbH. f Photograph of WS₂ monolayer film grown on a 2-inch sapphire substrate (left panel). The right panel shows the transfer characteristics of a representative WS₂ exhibiting a typical n-type nature. Reproduced with permission [76]. Copyright 2021, American Chemical Society. g Optical image of a p-type WSe₂, grown over a 2-inch sapphire wafer (left). The optical microscopic image of fabricated FET arrays (middle), and corresponding electrical characteristics clearly exhibit the p-nature (right). Reproduced with permission [77]. Copyright 2023, Wiley‐VCH GmbH. h Photograph and microscopic image of 2H MoTe₂ synthesized on 1-inch wafer and 1 T′/2H/1 T′ heterophase MoTe₂ based FET array fabricated with a phase-engineering method. The right panel shows the obtained electrical characteristics of the fabricated devices [78]. Copyright 2021, American Association for the Advancement of Science

Fig. 4

Use of 2D semiconductors in CMOS electronics. a Schematics representation showing the challenges associated with the typical ion implantation-based doping which leads to extensive damage in their lattice. b The strategies to realize the 2D materials-based CMOS electronics. The integration of two dissimilar 2D semiconductors (p- and n-type) nearby with a selective transfer on the same substrate to fabricate interconnected p- and n-channel FETs is one approach. Alternatively, selective conversion via treating the specific area of the same TMD via different approaches to tune charge carrier polarity type

Fig. 5

Fabrication of 2D semiconductors-based CMOS devices via transfer-based approach. a n-MoS₂ and a p-type WSe₂ flakes placed nearby on a SiO₂/p⁺-Si substrate using mechanical exfoliation and imprint-transfer-based approach. Circuit layout and the schematic diagram of the fabricated CMOS device. The 3D illustration of MoS₂ and WSe₂-based hetero-CMOS inverter in which SiO₂/p⁺-Si worked as a universal gate. The obtained output characteristics of the fabricated device. Reproduced with permission [115]. Copyright 2015, American Chemical Society. b Schematic illustration of a flexible CMOS complementary inverter developed by integrating CVD MoS₂-based n-MOS with Si nanomembrane-based p-MOS on a plastic substrate (left). Corresponding photographic (inset) and SEM images (middle) of the developed device unit. The right panel shows the output characteristics, of p-type TFT and n-type TFT obtained with scanning V_GS = − 3 to 0 V for p-MOS, and 0 to + 3 V for n-MOS. Reproduced with permission [50]. Copyright 2016, Wiley‐VCH GmbH

Fig. 6

CMOS devices developed by selective polarity conversion of the same TMDs via various surface treatment approaches. a Schematic illustrations of the 2H and 1 T- phase WSe₂ and a WSe₂ logic inverter. The charge carrier polarity in one WSe₂ channel was converted to n-type with Cs contact doping. The below plots represent the STS scans of pristine and Cs-modified WSe₂ including the obtained output characteristic. Reproduced with permission [113]. Copyright 2021, Springer Nature. b Schematic representation of the oxygen plasma-based doping approach to dope MoS₂ crystal (top). Illustration of a lateral p–n junction created with area selective oxygen plasma doping in MoS₂. The right panel shows the I–V characteristics of the fabricated p-n diode. Reproduced with permission [119]. Copyright 2021, IOP publishing. c Schematic illustration and optical image of a CMOS inverter fabricated with CVD-grown single MoTe₂ crystal. The charge carrier polarity in MoTe₂ was modulated by using an interfacial Al₂O₃ layer. Bottom plots represent the transfer characteristics of TFTs fabricated with bare and Al₂O₃ coated MoTe₂. The bottom right plots show the voltage transfer characteristics (VTC) of the fabricated CMOS inverter. Reproduced with permission [59]. Copyright 2019, Willey‐VCH GmbH. d Schematic representation of realizing the n- and p-type electrical polarity in mechanically exfoliated WSe₂ flakes. The thermally evaporated metal onto the WSe₂ lattice resulted in defects and damage, which provided n-doping effects. In contrast, the FETs fabricated with transferred metal exhibited a clean and sharp interface that resulted in intrinsic p-type electrical characteristics. Reproduced with permission [125]. Copyright 2020, Springer Nature. e The photo-induced polarity conversion in MoTe₂. The transfer characteristics of 2H-MoTe₂ back-gated FETs under the exposure of the UV laser (λ = 355 nm, left) and a visible laser (λ = 532 nm, right). The transfer characteristics exhibited n-type doping for red and p-type doping for blue light exposure. Reproduced with permission [111]. Copyright 2020, Springer Nature. f The chemical treatment-based doping in WSe₂ crystals with 4-NBD for p-type and DEA molecules for n-doping. The corresponding FET structure and obtained electrical characteristics in the fabricated devices. Reproduced with permission [114]. Copyright 2019, Willey‐VCH Verlag GmbH

Fig. 7

2D materials-based flexible CMOS devices. a Schematic representation of a flexible inverter fabricated with transferred MoS₂ and monolayer films. Reproduced with permission [18]. Copyright 2016, Willey‐VCH Verlag GmbH. b Photograph of a rollable logic circuit fabricated with MOCVD grown large area MoS₂ films. The enlarged view represents the NOT and NAND logic. Reproduced with permission [92]. Copyright 2018, Willey‐VCH Verlag GmbH. c The circuit layout and digital photographs of various integrated multistage circuits such as inverters, NOR gates, NAND gates, SRAMs, AND gates, and five-stage ring oscillators. These logic circuits were developed with large area MoS₂ grown by the MOCVD approach. Reproduced with permission [15]. Copyright 2020, Springer Nature. d The circuit layout and a photographic image of a flexible MoS₂-based artificial retina mounted on a contact lens. The schematic representation presented at left shows the device structure of a PRO developed with large area MoS₂. Reproduced with permission [144]. Copyright 2023, American Chemical Society. e Schematic representation of a CMOS inverter consisting of n-type MoS₂ and p-type WSe₂-FETs on flexible substrates. The large area MoS₂ and WSe₂ was synthesized by CVD and MOCVD approaches acting n-type and p-type channel materials, respectively. The digital photograph and the obtained electrical characteristics of the fabricated device. Reproduced with permission [145]. Copyright 2024, Willey‐VCH Verlag GmbH. f Photograph of a bent logic device developed with MOCVD grown large area MoS₂ film. The voltage transfer- and gain-characteristics of a NOT logic device operated under different V_dd. The photographs presented right side represent the repeated flexibility in the fabricated logic devices. Reproduced with permission [71]. Copyright 2023, Springer Nature

Fig. 8

Vertically integrated CMOS electronics. a Schematic illustration of the vertical integration of a monolayer MoS₂ FET on top of p-channel Si FinFET for realization of a CMOS inverter (left panel). The right panel shows the optical image of the fabricated 3D CMOS inverter. Reproduced with permission [161]. Copyright 2023, Springer Nature. b A 3D schematic and corresponding cross-sectional device layout of a vertically integrated graphene and MoS₂-based electronics. Reproduced with permission [164]. Copyright 2012, Springer Nature. c Schematic representation of the vertically integrated three-layer FETs organized by layer-by-layer stacking of graphene MoS₂ and h-BN. The used MoS₂ crystals were grown by the CVD approach, whereas graphene and h-BN were exfoliated mechanically. The right panel shows the obtained electrical characteristics. Reproduced with permission [162]. Copyright 2020, Wiley‐VCH GmbH. d Microscopic image and corresponding schematic representation of a two-tier CMOS circuit monolithically integrated with p- and n-channel WSe₂ FETs. Reproduced with permission [26]. Copyright 2024, Springer Nature. e Schematic representation of the vertically integrated 2D materials-based 3D logic electronic including SRAM and NAND gate. The right panel shows the dynamic NAND performance of the fabricated device. Reproduced with permission [12]. Copyright 2024, Springer Nature. f Device layout of a M3D-integrated AI processor designed with combining WSe₂/h-BN-based memristors and MoS₂-based FETs. The right panels show the complete device and a high-resolution image of a vertically stacked device. Reproduced with permission [13]. Copyright 2023, Springer Nature

Fig. 9

Challenges associated with the development of 2D materials-based CMOS. a Technological issues b Performance assessment of the p- and n-MOS units of the reported CMOS devices utilizing 2D materials

Fig. 10

Strategies to address the challenges hindering the commercialization of 2D materials-based CMOS electronics. a The use of transferred gate dielectric for the realization of large-area devices with high performance. Schematics representation showing the process-flow for the transferring wafer scale gate dielectric. The below panel shows corresponding optical images. The right panel shows the optical image and corresponding output versus input-voltage characteristics of the fabricated logic devices. Reproduced with permission [210]. Copyright 2023, Springer Nature. b The industrial compatible 2D materials transfer process. Schematic representation of the process steps involved in the wafer scale transfer of 2D materials. Reproduced with permission [240]. Copyright 2021, Springer Nature. c The strategy to achieve a wafer-level synthesis of 2D material at low temperatures. Schematic representation of the synthesis chamber, the optical images of synthesized 2D materials (e.g., MoS₂) on ultrathin glass and flexible polymeric substrates. Reproduced with permission [71]. Copyright 2023, Springer Nature

Fig. 11

Different research paths for realizing 2D materials-based CMOS electronic at the industrial standard with highlighting associated challenges and potential strategies to overcome them